M30626FJPFP#U5C Renesas Electronics America, M30626FJPFP#U5C Datasheet - Page 79

• Manufacturer Part Number: M30626FJPFP#U5C
• Description: IC M16C MCU FLASH 512K 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 8.2
Example 1
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
The address bus and the chip select signal both change state between
these two cycles.
Example 3
NOTES :
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
The address bus changes state but the chip select signal does not
change state
Address bus
Address bus
Read signal
Read signal
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
Data bus
Data bus
may be extended more than two cycles depending on a combination of these examples.
Jan 10, 2006
BCLK
BCLK
CSi
CSj
CSi
Access to the external
Access to the external
area indicated by CSi
area indicated by CSi
Example of Address Bus and CSi Signal Output in 1-Mbyte mode
Address
Address
Data
Data
Page 62 of 390
Address
Address
Access to the same
external area
Access to the external
area indicated by CSj
Data
Data
Example 2
Example 4
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The chip select signal changes state but the address bus does not
change state
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
Neither the address bus nor the chip select signal changes state between
these two cycles
Address bus
Read signal
Address bus
Read signal
Data bus
Data bus
BCLK
BCLK
CSi
CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Address
Data
Data
Address
No access
Access to the internal
ROM or internal RAM
8. Bus