M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 116

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 10.10
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1
NOTES :
10.4.3.3
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. Shown above is the case where the PM21 bit in the PM2 register = 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 and CM1 registers per 16 bit with CM21=0 (on-chip oscillator stops).
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to “ 0” (oscillation stop and oscillation restart detection function disabled).
Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function
interrupt.
When the hardware reset, NMI interrupt or low voltage detection interrupt is used to exit stop mode, set all
ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to “000b” (interrupt
disabled) before setting the CM10 bit to “1”.
When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to “1” after the following
settings are completed.
When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is as
follows, in accordance with the CPU clock source setting before the microcomputer had entered stop mode.
Figure 10.10 shows the State Transition from Normal Operating Mode to Stop Mode and Wait Mode. Figure
10.11 shows the State Transition in Normal Operating Mode.
Table 10.8 shows a state transition matrix describing Allowed Transition and Setting. The vertical line shows
current state and horizontal line shows state after transition.
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
(5)
All oscillators stopped
(1) Set the ILVL2 to ILVL0 bits in the interrupt control registers to decide the peripheral priority level of
(2) Set the I flag to “1”.
(3) Start operation of peripheral function being used to exit wait mode.
Jan 10, 2006
When the sub clock is the CPU clock before entering stop mode : Sub clock
When the main clock is the CPU clock source before entering stop mode : Main clock divided by 8
When the on-chip oscillator clock is the CPU clock source before entering stop mode
the peripheral function interrupt.
Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to “0” by setting the
all ILVL2 to ILVL0 bits to “000b”.
When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when an
interrupt request is generated and the CPU clock is supplied again.
Stop mode
Stop mode
Stop mode
Stop mode
Exiting Stop Mode
State Transition to Stop Mode and Wait Mode
Interrupt
Page 99 of 390
CM10=1
CM10=1
CM10=1
CM10=1
Interrupt
Interrupt
Interrupt
(6)
(6)
(6)
(6)
(4)
When
low power
dissipation
mode
On-chip oscillator, On-chip
oscillator dissipation mode
Low-speed, low power
dissipation mode
When
low-
speed
mode
Medium-speed mode
(divided-by-8 mode)
Normal mode
Reset
High-speed, medium-
speed mode
PLL operation
mode
(NOTES 1, 2)
: On-chip oscillator clock divided by 8
Interrupt
WAIT
instruction
WAIT
instruction
WAIT
instruction
WAIT
instruction
Interrupt
Interrupt
Interrupt
Wait mode
Wait mode
Wait mode
Wait mode
10. Clock Generation Circuit
CPU operation stopped

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