M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 119

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
10.5
The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is
selected the CPU clock source. This prevents the CPU clock from stopping should the program crash. This
function is available when the main clock is selected as the CPU clock source.
When the PM21 bit in the PM2 register is set to “1” (clock change disabled), the following bits cannot be written
to:
When using the system clock protection function, set the CM05 bit in the CM0 register to “0” (main clock
oscillation) and CM07 bit to “0” (main clock as CPU clock source) and follow the procedure below.
When the PM21 bit is set to “1,” do not execute the WAIT instruction.
(1) Set the PRC1 bit in the PRCR register to “1” (write enable).
(2) Set the PM21 bit in the PM2 register to “1” (protects the clock).
(3) Set the PRC1 bit in the PRCR register to “0” (write disable).
The CM02 bit, CM05 bit and CM07 bit in the CM0 register
The CM10 bit and CM11 bit in the CM1 register
The CM20 bit in the CM2 register
All bits in the PLC0 register
System Clock Protection Function
Jan 10, 2006
Page 102 of 390
10. Clock Generation Circuit

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