M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 129

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 12.4
INTi (0 to 5) Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
3.
4.
5.
0
This bit can only be reset by w riting “0” (Do not w rite “1”).
To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
If the IFSRi bit (i = 0 to 5) in the IFSR register are “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
edge).
When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the LVL2 to
ILVL0
Set the POL bit in the S3IC or S4IC register to “0” (falling edge) w hen the IFSR6 bit in the IFSR register = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Jan 10, 2006
Interrupt Control Registers (2)
Bit Symbol
(b7-b6)
Symbol
INT3IC
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
ILVL0
ILVL1
ILVL2
POL
(b5)
IR
Page 112 of 390
(4)
Interrupt Priority Level Select Bit
Interrupt Request Bit
Polarity Select Bit
Reserved Bit
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
(2)
Bit Name
005Dh to 005Fh
Address
0044h
0048h
0049h
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Set to “0”
After Reset
XX00X000b
XX00X000b
XX00X000b
XX00X000b
Function
(3, 5)
12. Interrupt
RW
RW
RW
RW
RW
RW
RW
(1)

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