M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 203

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.10
UARTi Special Mode Register (i=0 to 2)
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
Jan 10, 2006
1.
2.
3.
4.
1. When using multiple transfer clock output pins, make sure the follow ing conditions are met:
The BBS bit is set to “0” by w riting “0” in a program (Writing “1” has no ef f ect).
Underf low signal of Timer A 3 in UA RT0, underf low signal of Timer A 4 in UA RT1, underf low signal of Timer A 0 in
UA RT2.
When a transf er begins, the SSS bit is set to “0” (Not synchronized to RXDi).
The f unction of the bit 3 varies depending on the product.
If the product is M3062LFGPFP or M3062LFGPGP, the bit 3 becomes the LSY N bit.
If the product is other than M3062LFGPFP and M3062LFGPGP, the bit 3 is reserved. Theref ore, set it to 0.
When the LSY N bit is set to “1” and the SCLi pin outputs an "L" level signal, the data bit, such as the P6_2 bit in the P6
register f or SCL0 pin, the P6_6 bit in the P6 register f or SCL1 pin, and the P7_1 bit in the P7 register f or SCL2 pin, is set
to “1”.
CKDIR bit in the U1MR register = 0 (internal clock)
(The LSY N bit is an SCLL sync output enable bit.)
UCON and UiSMR Registers
Bit Symbol
Page 186 of 390
Bit Symbol
U0SMR to U2SMR
LSY N
A BSCS
CLKMD0
CLKMD1
U0RRM
U1RRM
(b3)
A CSE
A BC
U0IRS
U1IRS
BBS
SSS
(b7)
RCSP
IICM
(b7)
—
—
—
Symbol
(4)
(4)
Symbol
UCON
I
A rbitration Lost Detecting Flag
Control Bit
Bus Busy Flag
Reserved Bit
SCLL sync output enable bit
Bus Collision Detect Sampling
Clock Select Bit
A uto Clear Function Select Bit
of Transmit Enable Bit
Transmit Start Condition Select
Bit
Nothing is assigned.
When w rite, set to “0”. When read, its content is indeterminate.
2
UART0 Transmit Interrupt Factor
Select Bit
UART1 Transmit Interrupt Factor
Select Bit
UART0 Continuous Receive
Mode Enable Bit
UART1 Continuous Receive
Mode Enable Bit
UART1 CLK/CLKS Select Bit 0
UART1 CLK/CLKS Select Bit 1
Separate UART0
______
CTS/
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate.
C Mode Select Bit
_____
RTS
Bit
Bit Name
Bit Name
036Fh, 0373h, 0377h
Address
03B0h
A ddress
(1)
0 : Other than I
1 : I
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : STA RT condition detected (busy)
Set to “0”
0 : Disable
1 : Enable
0 : Rising edge of transf er clock
1 : Underf low signal of Timer A j
0 : No auto clear f unction
1 : A uto clear at occurrence of bus collision
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective w hen CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins
0 : CTS/
1 : CTS
2
C mode
function selected
_____
_____
(CTS0 supplied from the P6_4 pin)
/RTS
_____
RTS
_____
shared pin
separated
2
C mode
After Reset
X0000000b
Function
Function
(3)
A f ter Reset
X0000000b
(2)
17. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
—
RW
RW
RW
RW
RW
RW
RW
RW
—
(1)