M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 209

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.13
The above timing diagram applies to the case where the register bits are set as follows:
(1) Example of Transmit Timing (when internal clock is selected)
(2) Example of Receive Timing (when external clock is selected)
The above timing diagram applies to the case where the register bits are set
as follows:
fEXT: frequency of external clock
· CKDIR bit in UiMR register = 0 (internal clock)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data
· UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
TE bit in
UiC1 register
TI bit in
UiC1 register
CTSi
CLK
TXDi
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
RE bit in
UiC1 register
TE bit in
UiC1 register
TI bit in
UiC1 register
RTSi
CLKi
RXDi
RI bit in
UiC1 register
IR bit in
SiRIC register
OER flag in UiRB
register
Transfer clock
· CKDIR bit in UiMR register = 1 (external clock)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive
i = 0 to 2
i=0 to 2
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
i
Jan 10, 2006
“H”
“1”
“0”
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
Transmit and Receive Operation
“H”
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
Data is transferred from the UARTi
receive register to the UiRB register
Dummy data is set in the to UiTB register
Data is set in the UiTB register
D0 D1 D2 D3 D4 D5 D6 D7
Page 192 of 390
D0 D1 D2 D3 D4 D5 D6 D7
taken in at the rising edge of the transfer clock)
data taken in at the rising edge of the transfer clock)
Set to “0” by an interrupt request acknowledgement or by program
Data is transferred from the UiTB register to the UARTi transmit register
T
Data is transferred from the UiTB register to the UARTi transmit register
CLK
1 / fEXT
Received data is taken in
Tc
Read by the UiRB register
Pulse stops because an “H” signal is
applied to CTSi
Set to “0” by an interrupt request acknowledgement or by program
D0 D1 D2 D3 D4 D5
An “L” signal is applied when
the UiRB register is read
D0 D1 D2 D3 D4 D5 D6 D7
Make sure the following conditions are met when input to
the CLKi pin before receiving data is high:
· TE bit in UiC0 register = 1 (transmit enabled)
· RE bit in UiC0 register = 1 (receive enabled)
· Write dummy data to the UiTB register
D6
TC = TCLK = 2(n + 1) / fj
D7
fj: frequency of UiBRG count source
n: value set to UiBRG register
(f1SIO, f2SIO, f8SIO, f32SIO)
D0 D1 D2 D3 D4 D5
Pulse stops because the TE bit is set to “0”
D0 D1 D2 D3 D4 D5 D6 D7
17. Serial Interface
D6

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