M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 226

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 17.13
NOTES:
i = 0 to 2
Function
Factor of Interrupt Number
6, 7 and 10
Factor of Interrupt Number
15, 17 and 19
Factor of Interrupt Number
16, 18 and 20
Timing for Transferring Data
From the UART Reception
Shift Register to the UiRB
Register
UARTi Transmission Output
Delay
Functions of P6_3, P6_7 and
P7_0 Pins
Functions of P6_2, P6_6 and
P7_1 Pins
Functions of P6_1, P6_5 and
P7_2 Pins
Noise Filter Width
Read RXDi and SCLi Pin
Levels
Initial Value of TXDi and
SDAi Outputs
Initial and End Values of SCLi −
DMA1 Factor
Store Received Data
Read Received Data
1. If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled).
3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5. See Figure 17.28 STSPSEL Bit Functions .
6. See Figure 17.26 Transfer to UiRB Register and Interrupt Timing .
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).
inadvertently be set to “1” (interrupt requested). (Refer to 24.7 Interrupt )
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).
Jan 10, 2006
(1, 5, 7)
(6)
(1, 6)
(1, 6)
I
2
C Mode Functions
Clock Synchronous Serial I/O
Mode (SMD2 to SMD0 = 001b,
IICM = 0)
−
UARTi transmission
Transmission started or
completed (selected by UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TXDi output
RXDi input
CLKi input or output selected
15ns
Possible when the corresponding
port direction bit = 0
CKPOL = 0 (H)
CKPOL = 1 (L)
UARTi reception
1st to 8th bits of the received data
are stored into bits 7 to 0 in the
UiRB register
The UiRB register status is read
Page 209 of 390
I
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 0
(No clock delay)
Start condition detection or stop condition detection
(See Table 17.14 STSPSEL Bit Functions )
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
Delayed
SDAi input/output
SCLi input/output
− (Cannot be used in I
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I
H
Acknowledgment detection (ACK)
1st to 8th bits of the received data are
stored into bits 7 to 0 in the UiRB
register
2
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
CKPH = 1
(Clock delay)
L
2
C mode)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(No clock delay)
UARTi transmission
Rising edge of SCLi
9th bit
UARTi reception
Falling edge of SCLi 9th bit
Falling edge of SCLi
9th bit
H
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB register.
8th bit is stored into bit 8 in the UiRB
register.
2
C mode
(2)
17. Serial Interface
CKPH = 1
(Clock delay)
UARTi transmission
Falling edge of SCLi
next to the 9th bit
Falling and rising
edges of SCLi 9th
bit
L
1st to 8th bits are
stored into bits 7 to
0 in the UiRB
register
Bits 6 to 0 in the
UiRB register
read as bits 7 to 1.
Bit 8 in the UiRB
register is read as
bit 0.
(3)
(4)
are