M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 232

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.4
Table 17.15
NOTES:
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable.
Table 17.15 lists the Special Mode 2 Specifications. Table 17.16 lists the Registers to Be Used and Settings in
Special Mode 2. Figure 17.29 shows Serial Bus Communication Control Example (UART2).
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the
receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
not change.
Jan 10, 2006
Special Mode 2
Item
Special Mode 2 Specifications
Page 215 of 390
Transfer data length: 8 bits
• Master mode
• Slave mode
Controlled by input/output ports
Before transmission can start, meet the following requirements
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register = 0 (data present in UiTB register)
Before reception can start, meet the following requirements
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data from
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
Overrun error
Clock phase setting
the UiTB register to the UARTi transmit register (at start of transmission)
from the UARTi transmit register
completion of reception)
CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
Selectable from four combinations of transfer clock polarities and phases
(2)
Specification
(1)
(1)
17. Serial Interface