M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 234

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 17.16
NOTES:
i = 0 to 2
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
Register
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in Special Mode 2.
(3)
(3)
(3)
in the UCON register.
Jan 10, 2006
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiERE
0 to 7
0 to 7
CKPH
NODC
0, 2, 4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7 Set to “0”
Registers to Be Used and Settings in Special Mode 2
(1)
Bit
(1)
, UiLCH,
Page 217 of 390
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to “001b”
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TXDi pin output format
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt factor
Set to “0”
Set to “0”
Set to “0”
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
Set to “0”
Set to “0”
Set to “0”
Select UART0 and UART1 transmit interrupt factor
Set to “0”
Invalid because CLKMD1 = 0
(2)
Function
17. Serial Interface

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