M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 241

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.34
(1) Transmit Timing
Transfer clock
TE bit in U2C1
register
TI bit in U2C1
register
TXD2
Parity Error signal
returned from
Receiving end
RXD2
TXEPT bit in U2C0
register
IR bit in S2TIC
register
Transfer clock
RE bit in U2C1
register
Transmit Waveform
from the
Transmitting end
TXD2
RXD2 pin level
RI bit in U2C0
register
IR bit in S2RIC
register
(2) Receive Timing
The above timing diagram applies to the case where data is
transferred in the direct format.
NOTES:
pin level
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit.
2. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
3. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
The above timing diagram applies to the case where data is
transferred in the direct format.
Jan 10, 2006
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
TxD2 pin and parity error signal from the receiving end, is generated.
transmitting end and parity error signal from the TxD2 pin, is generated.
(2)
(1)
“1”
“0”
“1”
“0”
“1”
“0”
Transmit and Receive Timing in SIM Mode
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
Start
Start
Page 224 of 390
ST
ST
ST
bit
ST
bit
D0
D0
D0
D0
D1
D1
D1
D1
Tc
Tc
D2
D2
D2
D2
D3
D3
D3
D3
Data is written to the UARTi register
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
Parity
Parity
bit
bit
P
P
P
P
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
SP
SP
SP
SP
Set to “0” by an interrupt request acknowledgement or by program
Set to “0” by an interrupt request acknowledgement or by program
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Stop
Stop
bit
bit
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
ST
ST
ST
ST
An interrupt routine
detects “H” or “L”
(f1SIO, f2SIO, f8SIO, f32SIO)
Data is transferred from the UiTB
register to the UARi transmit register
(Note 1)
An “L” signal is applied from the
SIM card due to a parity error
D0
D0
D0
D0
Read the U2RB register
D1
D1
D1
D1
TxD2 provides “L” output
due to a parity error
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
An interrupt routine detects “H” or “L”
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
P
P
P
P
17. Serial Interface
SP
SP
SP
SP