M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 291

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 22.2
Figure 22.3
ROM Code Protect Control Address
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
1 1
When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or
rew riting in parallel I/O mode.
Set the bit 5 to bit 0 to “111111b” w hen the ROMCP1 bit is set to a value other than “11b”.
If the bit 5 to bit 0 are set to values other than “111111b”, the ROM code protection may not become active by setting
the ROMCP1 bit to a value other than “11b”.
To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode
or CPU rew rite mode.
The ROMCP address is set to “FFh” w hen a block, including the ROMCP address, is erased.
When a value of the ROMCP address is “00h” or “FFh”, the ROM code protect function is disabled.
Jan 10, 2006
b3
1
b2 b1
1 1 1
ROMCP Register
Address for ID Code Stored
b0
0FFFDFh to 0FFFDCh
0FFFE3h to 0FFFE0h
0FFFE7h to 0FFFE4h
0FFFEBh to 0FFFE8h
0FFFEFh to 0FFFECh
0FFFF3h to 0FFFF0h
0FFFF7h to 0FFFF4h
0FFFFBh to 0FFFF8h
0FFFFFh to 0FFFFCh
Bit Symbol
ROMCP1
ROMCP
(b5-b0)
Symbol
Page 274 of 390
—
Address
Reserved Bit
ROM Code Protect Level 1 Set
Bit
(1, 2, 3, 4)
(5)
Address
0FFFFFh
Bit Name
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ROMCP
Undefined instruction vector
Overflow vector
BRK instruction vector
Address match vector
Single step vector
Watchdog timer vector
DBC vector
NMI vector
Reset vector
b7 b6
0 0 :
0 1 :
1 0 :
1 1 : ROM code protection inactive
Set to “1”
4 bytes
ROM code protection active
Factory Setting
Function
FFh
(4)
22. Flash Memory Version
RW
RW
RW