M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 308

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
22.3.6
22.3.7
22.3.7.1
22.3.7.2
22.3.7.3
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to
“0” (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and
erase. This helps prevent data from being inadvertently written to or erased from the flash memory.
The lock bit status is set to “0” (locked) by executing the lock bit program command and to “1” (unlocked) by
erasing the block. The lock bit status cannot be set to “1” by any commands.
The lock bit status can be read by the read lock bit status command.
The lock bit function is disabled by setting the FMR02 bit to “1”. All blocks are unlocked. However, individual
lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to “0”. Lock bit
status is retained.
If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to “1”, the target
block or all blocks are erased regardless of lock bit status. The lock bit status of each block are set to “1” after
an erase operation is completed.
Refer to 22.3.5 Software Commands for details on each command.
The status register indicates the flash memory operation state and whether or not an erase or program operation
is completed as expected. The FMR00, FMR06 and FMR07 bits in the FMR0 register indicate status register
states.
Table 22.5 shows the Status Register.
In EW0 mode, the status register can be read when the followings occur.
The sequence status indicates the flash memory operation state. It is set to “0” while the program, block erase,
erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is
set to “1”.
Refer to 22.3.8 Full Status Check.
Refer to 22.3.8 Full Status Check.
•
•
•
•
Jan 10, 2006
When the lock bit status is set to “0”, the block is locked (block is protected against program and erase).
When the lock bit status is set to “1”, the block is not locked (block can be programmed or erased).
Any even address in the user ROM area is read after writing the read status register command.
Any even address in the user ROM area is read from when the program, block erase, erase all unlocked
block, or lock bit program command is executed until when the read array command is executed.
Data Protect Function
Status Register
Sequence Status (SR7 and FMR00 Bits)
Erase Status (SR5 and FMR07 Bits)
Program Status (SR4 and FMR06 Bits)
Page 291 of 390
22. Flash Memory Version