M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 383

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
24.7
24.7.1
24.7.2
24.7.3
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads
interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the
interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is cleared to “0”. This factors a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to “0000h” after
reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the program may go
out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first and
only the first instruction after reset, all interrupts including NMI interrupt are disabled.
Interrupt
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Jan 10, 2006
The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC1 via a
resistor (pull-up).
The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the P8_5
bit can only be read when determining the pin level in NMI interrupt routine.
Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin goes
low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip does not
drop. In this case, normal condition is restored by an interrupt generated thereafter.
The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles + 300
ns or more.
Reading address 00000h
Setting the SP
The NMI Interrupt
Page 366 of 390
24. Precautions