IC MICROCONTROLLER 16BIT 100TQFP

SAB-C161PI-LF CA

Manufacturer Part NumberSAB-C161PI-LF CA
DescriptionIC MICROCONTROLLER 16BIT 100TQFP
ManufacturerInfineon Technologies
SeriesC16xx
SAB-C161PI-LF CA datasheet
 


Specifications of SAB-C161PI-LF CA

Core ProcessorC166Core Size16-Bit
Speed20MHzConnectivityEBI/EMI, I²C, SPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o76
Program Memory TypeROMlessRam Size3K x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 4x10b
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case100-LFQFPPackagesPG-TQFP-100
Max Clock Frequency20.0 MHzSram (incl. Cache)3.0 KByte
A / D Input Lines (incl. Fadc)4Program Memory0.0 KByte
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Program Memory Size-Other namesB161PILFCAXT
SAB-C161PI-LF CA
SAB-C161PI-LFCAINTR
SABC161PILFCAXT
SP000014344
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C161PI
Microcontrollers
C166 Family
16-Bit Single-Chip Microcontroller
C161PI
Data Sheet 1999-07
Preliminary

SAB-C161PI-LF CA Summary of contents

  • Page 1

    C161PI Microcontrollers C166 Family 16-Bit Single-Chip Microcontroller C161PI Data Sheet 1999-07 Preliminary ...

  • Page 2

    ... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Tech- nologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...

  • Page 3

    C166 Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C161PI 16-Bit Microcontroller • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation ...

  • Page 4

    ... This document describes the SAB-C161PI-LM, the SAB-C161PI-LF, the SAF-C161PI- LM and the SAF-C161PI-LF. For simplicity all versions are referred to by the term C161PI throughout this document. Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • ...

  • Page 5

    Introduction The C161PI is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161PI derivative is especially ...

  • Page 6

    Pin Configuration MQFP Package (top view) P5.2/AN2 1 P5.3/AN3 2 P5.14/T4EUD 3 P5.15/T2EUD XTAL1 6 XTAL2 P3.0/SCL0 9 P3.1/SDA0 10 P3.2/CAPIN 11 P3.3/T3OUT 12 P3.4/T3EUD 13 P3.5/T4IN 14 P3.6/T3IN 15 P3.7/T2IN 16 ...

  • Page 7

    Pin Configuration TQFP Package (top view) P5.14/T4EUD 1 P5.15/T2EUD XTAL1 4 XTAL2 P3.0/SCL0 7 P3.1/SDA0 8 P3.2/CAPIN 9 P3.3/T3OUT 10 P3.4/T3EUD 11 P3.5/T4IN 12 P3.6/T3IN 13 P3.7/T2IN 14 P3.8/MRST 15 P3.9/MTSR 16 ...

  • Page 8

    Table 1 Pin Definitions and Functions Symbol Pin Pin Num. Num. TQFP MQFP P5 P5 P5.1 98 100 P5 P5.3 100 2 P5. P5. XTAL1 4 6 XTAL2 5 7 Data Sheet ...

  • Page 9

    Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Num. Num. TQFP MQFP P3.8 ...

  • Page 10

    Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Num. Num. TQFP MQFP WR/ ...

  • Page 11

    Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Num. Num. TQFP MQFP PORT0 P0L.0-7 38- 40 P0H.0-7 48- 50 PORT1 P1L.0-7 56- 58 P1H.0-7 66- 68 Data ...

  • Page 12

    Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Num. Num. TQFP MQFP RSTIN 76 78 RST 77 79 OUT NMI 78 80 Data Sheet Input Function Outp. I/O Reset Input with Schmitt-Trigger characteristics. A low level at this ...

  • Page 13

    Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Num. Num. TQFP MQFP ...

  • Page 14

    Table 1 Pin Definitions and Functions (continued) Symbol Pin Pin Num. Num. TQFP MQFP 6, 23, 8, 25, DD 37, 39, 47, 49, 65 22, 5, 24, SS 36, 38, 46, 48, 64, 74 66, 76 ...

  • Page 15

    Functional Description The architecture of the C161PI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the ...

  • Page 16

    ... KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. ...

  • Page 17

    External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...

  • Page 18

    Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...

  • Page 19

    The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...

  • Page 20

    Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C161PI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...

  • Page 21

    Table 2 C161PI Interrupt Nodes Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 ...

  • Page 22

    The C161PI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...

  • Page 23

    General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...

  • Page 24

    T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD Figure 6 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module ...

  • Page 25

    The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based ...

  • Page 26

    Real Time Clock The Real Time Clock (RTC) module of the C161PI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...

  • Page 27

    ... In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via registers P5DIDIS (Port 5 Digital Input Disable). Data Sheet 25 & ...

  • Page 28

    Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...

  • Page 29

    ... The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows ...

  • Page 30

    ... Parallel Ports The C161PI provides lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...

  • Page 31

    ... BAND, BOR, AND/OR/XOR direct bit with direct bit BXOR BCMP Compare direct bit to direct bit BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 ...

  • Page 32

    ... Software Reset IDLE Enter Idle Mode PWRDN Enter Power Down Mode (supposes NMI-pin being low) SRVWDT Service Watchdog Timer DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence ...

  • Page 33

    ... The following table lists all SFRs which are implemented in the C161PI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-Peripherals (I²C) are marked with the letter “X” in column “ ...

  • Page 34

    Table 5 C161PI Registers, Ordered by Name (continued) Name Physical Address CC12IC b FF90 H CC13IC b FF92 H CC14IC b FF94 H CC15IC b FF96 H CP FE10 H CRIC b FF6A H CSP FE08 H DP0L b F100 ...

  • Page 35

    ... Port 1 High Reg. (Upper half of PORT1 Port 2 Register H E2 Port 3 Register H E4 Port 4 Register (7 bits Port 5 Register (read only Port 5 Digital Input Disable Register H E6 Port 6 Register (8 bits PEC Channel 0 Control Register H 61 PEC Channel 1 Control Register H 62 PEC Channel 2 Control Register H 63 ...

  • Page 36

    Table 5 C161PI Registers, Ordered by Name (continued) Name Physical Address RTCH F0D6 H RTCL F0D4 H S0BG FEB4 H S0CON b FFB0 H S0EIC b FF70 H S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C H S0TBUF ...

  • Page 37

    Table 5 C161PI Registers, Ordered by Name (continued) Name Physical Address T14REL F0D0 H T2 FE40 H T2CON b FF40 H T2IC b FF60 H T3 FE42 H T3CON b FF42 H T3IC b FF62 H T4 FE44 H T4CON ...

  • Page 38

    Absolute Maximum Ratings Table 6 Absolute Maximum Rating Parameters Parameter Storage temperature Voltage on pins with DD respect to ground ( ) SS Voltage on any pin with respect to ground ( ) SS Input current on any pin during ...

  • Page 39

    ... Unit Notes V Active mode MHz CPUmax V PowerDown mode V Active mode MHz CPUmax V PowerDown mode V Reference voltage Per pin Pin drivers in fast edge mode (PDCR.BIPEC = ’0’) pF Pin drivers in reduced edge mode (PDCR.BIPEC = 3) ’1’) °C SAB-C161PI... °C SAF-C161PI... °C SAK-C161PI... 1999-07 ...

  • Page 40

    Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161PI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...

  • Page 41

    DC Characteristics (Standard Supply Voltage Range) (continued) (Operating Conditions apply) Parameter Output low voltage (all other outputs) 1) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 1) Output high voltage (all other outputs) Input leakage ...

  • Page 42

    ... Power-down mode supply current (5V) with RTC running Power-down mode supply current (5V) with RTC disabled 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. ...

  • Page 43

    DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage RSTIN Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, ...

  • Page 44

    ... RTC running Power-down mode current (3V) with RTC disabled 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) These parameters describe the RSTIN pullup, which equals a resistance of ca 250 K . ...

  • Page 45

    The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested The oscillator also contributes to the total supply current. The given ...

  • Page 46

    Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet &3, I DD5max I DD5typ I DD3max I ID5max I DD3typ I ID5typ I ID3max I ID3typ 25 [MHz] CPU ...

  • Page 47

    AC Characteristics Definition of Internal Timing The internal operation of the C161PI is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the ...

  • Page 48

    Table 8 C161PI Clock Generation Modes P0.15-13 CPU Frequency I I (P0H.7- CPU OSC OSC OSC OSC ...

  • Page 49

    The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As ...

  • Page 50

    ... Direct Drive When pins P0.15-13 (P0H.7-5) equal 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of directly follows the frequency of CPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock CPU ...

  • Page 51

    AC Characteristics External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Oscillator period SR OSC 2) High time Low time Rise time Fall time ...

  • Page 52

    Figure 13 External Clock Drive XTAL1 Note: The main oscillator is optimized for oscillation with a crystal within a frequency range of 4...16 MHz. When driven by an external clock signal it will accept the specified frequency range. Operation at ...

  • Page 53

    A/D Converter Characteristics (Operating Conditions apply) 4.0V (2.6V) AREF DD - 0.1V SS AGND SS Parameter Analog input voltage range Basic clock frequency Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC ...

  • Page 54

    Sample time and conversion time of the C161PI’s A/D Converter are programmable. The table below should be used to calculate the above timings. The limit values for must not be exceeded when selecting ADCTC. BC Table 9 A/D Converter Computation ...

  • Page 55

    Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at Figure 14 Input Output Waveforms For timing purposes a ...

  • Page 56

    AC Characteristics Multiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE ...

  • Page 57

    Multiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD ALE ...

  • Page 58

    Multiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS ...

  • Page 59

    AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE ...

  • Page 60

    Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD ALE ...

  • Page 61

    Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS 1) These parameters refer ...

  • Page 62

    ALE CSxL A22-A16 (A15-A8) BHE, CSxE 5HDG &\FOH BUS RD RdCSx :ULWH &\FOH BUS WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet Address 6 7 ...

  • Page 63

    ALE 38 CSxL A22-A16 (A15-A8) BHE, CSxE 6 5HDG &\FOH BUS RD RdCSx :ULWH &\FOH BUS WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet Address 7 ...

  • Page 64

    ALE CSxL A22-A16 (A15-A8) BHE, CSxE 5HDG &\FOH BUS RD RdCSx :ULWH &\FOH BUS WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet Address 6 7 ...

  • Page 65

    ALE 38 CSxL A22-A16 (A15-A8) BHE, CSxE 6 5HDG &\FOH BUS RD RdCSx :ULWH &\FOH BUS WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet Address 7 ...

  • Page 66

    AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, ...

  • Page 67

    Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge to CS ...

  • Page 68

    Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Address hold after RdCS, WrCS Data hold after WrCS 1) RW-delay and refer to the next following bus cycle (including an ...

  • Page 69

    AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, ...

  • Page 70

    Demultiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge to CS ...

  • Page 71

    Demultiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Address hold after RdCS, WrCS Data hold after WrCS 1) RW-delay and refer to the next following bus cycle (including an ...

  • Page 72

    ALE CSxL A22-A16 A15-A0 BHE, CSxE 5HDG &\FOH BUS (D15-D8) D7-D0 RD RdCSx :ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...

  • Page 73

    ALE 38 CSxL A22-A16 A15-A0 BHE, 6 CSxE 5HDG &\FOH BUS (D15-D8) D7-D0 RD RdCSx :ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 21 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet 16 ...

  • Page 74

    ALE CSxL A22-A16 A15-A0 BHE, CSxE 5HDG &\FOH BUS (D15-D8) D7-D0 RD RdCSx :ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL,WRH WrCSx Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...

  • Page 75

    ALE 38 CSxL A22-A16 A15-A0 BHE,CSxE 6 5HDG &\FOH BUS (D15-D8) D7-D0 RD RdCSx :ULWH &\FOH BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet 16 39 ...

  • Page 76

    AC Characteristics CLKOUT and READY (Standard Supply Voltage Range) (Operating Conditions apply) Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to ...

  • Page 77

    AC Characteristics CLKOUT and READY (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to ...

  • Page 78

    Running cycle 32 CLKOUT ALE Command RD, WR Sync READY 58 Async 3) READY Figure 24 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command ...

  • Page 79

    Package Outlines Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) Figure 25 Data Sheet 77 &3, 1999-07 ...

  • Page 80

    Package Outlines (continued) Plastic Package, P-TQFP-100-1 (SMD) (Plastic Thin Metric Quad Flat Package) Figure 26 Sorts of Packing Package outlines for tubes, trays, etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Data Sheet 78 ...

  • Page 81

    Data Sheet 79 &3, 1999-07 ...

  • Page 82

    ... Published by Infineon Technologies AG Data Sheet 80 &3, 1999-07 ...