SAF-C164CI-8EM CB Infineon Technologies, SAF-C164CI-8EM CB Datasheet

IC MCU 16BIT OTP MQFP-80-1

SAF-C164CI-8EM CB

Manufacturer Part Number
SAF-C164CI-8EM CB
Description
IC MCU 16BIT OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C164CI-8EM CB

Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
59
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
F164CI8EMCBNT
F164CI8EMCBXT
SAF-C164CI-8EMCB
SAF-C164CI-8EMCBINTR
SAF-C164CI-8EMCBTR
SAF-C164CI-8EMCBTR
SAFC164CI8EMCBXT
SP000103499
D at a S he e t, V 2. 0 , M ay 20 0 1
C 1 6 4C I/ SI
C 1 6 4C L/ SL
16 -B it S in gl e -C hi p Mi cro c on tro ll e r
Mi cro c on tr ol le rs
N e v e r
s t o p
t h i n k i n g .

Related parts for SAF-C164CI-8EM CB

SAF-C164CI-8EM CB Summary of contents

Page 1

cro c on tro cro ...

Page 2

... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...

Page 3

cro c on tro cro ...

Page 4

C164CI Revision History: Previous Version: Page Subjects (major changes since last revision) All Converted to Infineon layout 1 Operating frequency MHz 1 et al. References to Flash removed 1 Timer Unit with three timers 1, 12, 73 ...

Page 5

Single-Chip Microcontroller C166 Family C164CI/SI, C164CL/SL • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division ( ...

Page 6

... SAF-C164SI-8R[25]M SAK-C164CL-8R[25]M SAF-C164CL-8R[25]M SAK-C164SL-8R[25]M SAF-C164SL-8R[25]M SAK-C164CL-6R[25]M SAF-C164CL-6R[25]M SAK-C164SL-6R[25]M SAF-C164SL-6R[25]M SAK-C164CI-L[25]M SAF-C164CI-L[25]M SAK-C164CI-8EM SAF-C164CI-8EM 1) This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices starting with and including design step DA. For simplicity all versions are referred to by the term C164CI throughout this document. ...

Page 7

Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the ...

Page 8

Pin Configuration (top view AREF P5.4/AN4/T2EUD 2 P5.5/AN5/T4EUD 3 P5.6/AN6/T2IN 4 5 P5.7/AN7/T4IN P3.4/T3EUD 8 P3.6/T3IN 9 P3.8/MRST 10 P3.9/MTSR 11 P3.10/TxD0 12 P3.11/RxD0 13 P3.12/BHE/WRH 14 P3.13/SCLK 15 P3.15/CLKOUT/FOUT 16 P4.0/A16/CS3 ...

Page 9

Table 2 Pin Definitions and Functions Symbol Pin Input No. Outp P3.4 ...

Page 10

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp ...

Page 11

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp PORT0 IO P0L.0-7 29- 36 P0H.0-7 37-39, 42-46 Data Sheet Function External Access Enable pin. A low level at this pin during and ...

Page 12

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. PORT1 IO P1L.0-7 47-52, 57-59 P1H.0-7 59, 62-68 P1L.0 47 I/O P1L P1L.2 49 I/O P1L P1L.4 51 I/O P1L P1L.6 57 ...

Page 13

... A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT) ...

Page 14

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P8.0 72 I/O I P8.1 73 I/O O P8.2 74 I/O I P8 – AREF V 80 – AGND V 7, ...

Page 15

Functional Description The architecture of the C164CI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...

Page 16

Memory Organization The memory space of the C164CI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...

Page 17

External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...

Page 18

Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...

Page 19

The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...

Page 20

Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C164CI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...

Page 21

Table 3 C164CI Interrupt Nodes Source of Interrupt or PEC Service Request Fast External Interrupt 0 CC8IR Fast External Interrupt 1 CC9IR Fast External Interrupt 2 CC10IR Fast External Interrupt 3 CC11IR GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer ...

Page 22

Table 3 C164CI Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM 6 Timer 12 CAPCOM 6 Timer 13 CAPCOM 6 Emergency CC6EIR Data Sheet Request Enable Interrupt Flag Flag Vector T12IR T12IE T12INT T13IR T13IE T13INT CC6EIE ...

Page 23

The C164CI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...

Page 24

The Capture/Compare Unit CAPCOM2 The general purpose CAPCOM2 unit supports generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks ...

Page 25

The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences three 16-bit capture/compare channels plus one 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have ...

Page 26

General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...

Page 27

T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 Data Sheet U/D GPT1 Timer ...

Page 28

Real Time Clock The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...

Page 29

A/D Converter For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and ...

Page 30

Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...

Page 31

... Port 4 cannot be used. This will limit the external address space. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’ ...

Page 32

Parallel Ports The C164CI provides I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction ...

Page 33

Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on ...

Page 34

Power Management The C164CI provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C164CI into ...

Page 35

Instruction Set Summary Table 6 lists the instructions of the C164CI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the ...

Page 36

Table 6 Instruction Set Summary (cont’d) Mnemonic Description MOV(B) Move word (byte) data MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand with zero extension JMPA, JMPI, Jump absolute/indirect/relative if condition is ...

Page 37

Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C164CI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter ...

Page 38

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address C1MCFGn EFn6 H C1MCRn EFn0 H C1PCIR EF02 H C1UARn EFn2 H C1UGML EF08 H C1UMLM EF0C H CC10IC b FF8C H CC11IC b FF8E H CC16 FE60 H ...

Page 39

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address CC26IC b F174 H CC27 FE76 H CC27IC b F176 H CC28 FE78 H CC28IC b F178 CC29 FE7A H CC29IC b F184 ...

Page 40

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address CTCON b FF30 H DP0H b F102 H DP0L b F100 H DP1H b F106 H DP1L b F104 H DP3 b FFC6 H DP4 b FFCA H DP8 ...

Page 41

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address OPDAT EDC4 H P0H b FF02 H P0L b FF00 H P1H b FF06 H P1L b FF04 FFC4 FFC8 ...

Page 42

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address RTCH F0D6 H RTCL F0D4 H S0BG FEB4 H S0CON b FFB0 H S0EIC b FF70 H S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C H S0TBUF ...

Page 43

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address T12IC b F190 H T12OF F034 H T12P F030 H T13IC b F198 H T13P F032 H T14 F0D2 H T14REL F0D0 H T2 FE40 H T2CON b FF40 ...

Page 44

Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address XP3IC b F19E H ZEROS b FF1C H 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. Note: The three ...

Page 45

Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ( ) SS Input ...

Page 46

... > < C164CI/SI C164CL/SL Unit Notes V Active mode MHz CPUmax V PowerDown mode V Reference voltage 2)3) mA Per pin Pin drivers in default mode °C SAB-C164CI … °C SAF-C164CI … °C SAK-C164CI … - 0.5 V). The absolute sum of input overload V2.0, 2001-05 4)5) ...

Page 47

Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C164CI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...

Page 48

DC Characteristics (cont’d) (Operating Conditions apply) Parameter Input leakage current (all other) 6) RSTIN inactive current 6) RSTIN active current 9) RD/WR inact. current 9) RD/WR active current 9) ALE inactive current 9) ALE active current 9) Port 4 inactive ...

Page 49

Table 10 Current Limits for Port Output Drivers Port Output Driver Maximum Output Current I Mode ( Strong driver 10 mA Medium driver 4.0 mA Weak driver 0 output current above | OXnom For any group ...

Page 50

Power Consumption C164CI (OTP) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Sleep and ...

Page 51

Figure 8 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet C164CI/SI C164CL/SL I IDOmax I IDOtyp I PDRmax I PDOmax 12 ...

Page 52

I [mA] 100 Figure 9 Supply/Idle Current as a Function of Operating Frequency for ROM Derivatives Data Sheet C164CI/SI C164CL/SL I DD5max I DD5typ I IDX5max I IDX5typ 25 f [MHz] CPU ...

Page 53

I [mA] 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency for OTP Derivatives Data Sheet C164CI/SI C164CL/SL I DD5max I DD5typ I IDX5max I IDX5typ 25 f [MHz] CPU ...

Page 54

AC Characteristics Definition of Internal Timing The internal operation of the C164CI is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external ...

Page 55

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C164CI Clock Generation Modes 1) CLKCFG ...

Page 56

Due to this adaptation to the input clock the frequency locked to . The slight variation causes a jitter of OSC duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs ...

Page 57

Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the ...

Page 58

AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 External Clock Drive Characteristics Parameter Symbol t Oscillator period SR 40 OSC 2) t High time Low time Rise ...

Page 59

A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...

Page 60

During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final voltage level within After the end of the sample time t Values for the sample time S Sample ...

Page 61

Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at Figure 14 Input Output Waveforms V + 0.1 V ...

Page 62

Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 15 ...

Page 63

Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter RD, WR low time (no RW-delay valid data in (with RW-delay valid data in (no RW-delay) ALE low to valid data ...

Page 64

Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) ...

Page 65

ALE CSxL A21-A16 (A15-A8) BHE, CSxE t Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...

Page 66

ALE t 38 CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet t 16 ...

Page 67

ALE CSxL A21-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...

Page 68

ALE t 38 CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet t 16 ...

Page 69

AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, ...

Page 70

Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge to CS ...

Page 71

Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS 1) t RW-delay and refer to the next following ...

Page 72

ALE CSxL A21-A16 A15-A0 BHE, CSxE t Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet t ...

Page 73

ALE t 38 CSxL A21-A16 A15-A0 BHE CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 21 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE ...

Page 74

ALE CSxL A21-A16 A15-A0 BHE, CSxE t Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL,WRH WrCSx Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet t 16 ...

Page 75

ALE t 38 CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE ...

Page 76

AC Characteristics CLKOUT (Operating Conditions apply) Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge CLKOUT ALE Command RD, WR Figure 24 CLKOUT Timing Notes 1) ...

Page 77

External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C164CI can be accessed (during hold states external master like an asynchronous SRAM. Table 16 XRAM Access Timing (Operating Conditions apply) Parameter Address setup time ...

Page 78

Package Outlines P-MQFP-80-7 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 74 C164CI/SI C164CL/SL Dimensions in mm V2.0, 2001-05 ...

Page 79

... Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher Published by Infineon Technologies AG ...

Related keywords