IC MCU 16BIT MQFP-144

SAB-C167CR-LM HA+

Manufacturer Part NumberSAB-C167CR-LM HA+
DescriptionIC MCU 16BIT MQFP-144
ManufacturerInfineon Technologies
SeriesC16xx
SAB-C167CR-LM HA+ datasheet
 


Specifications of SAB-C167CR-LM HA+

Core ProcessorC166Core Size16-Bit
Speed25MHzConnectivityCAN, EBI/EMI, SPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o111
Program Memory TypeROMlessRam Size4K x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 16x10b
Oscillator TypeExternalOperating Temperature0°C ~ 70°C
Package / Case144- BSQFPData Bus Width16 bit
Data Ram Size4 KBInterface Type1xUSART, 1xSSC
Maximum Clock Frequency25 MHzNumber Of Programmable I/os111
Number Of Timers9Operating Supply Voltage5 V
Maximum Operating Temperature+ 70 CMounting StyleSMD/SMT
Minimum Operating Temperature0 COn-chip Adc10 bit, 16 Channel
PackagesPG-MQFP-144Max Clock Frequency25.0 MHz
Sram (incl. Cache)4.0 KByteCan Nodes1
A / D Input Lines (incl. Fadc)16Program Memory0.0 KByte
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Program Memory Size-Other namesB167CRLMHAZNP
B167CRLMHAZXP
SAB-C167CR-LMHA
SAB-C167CR-LMHA+
SAB-C167CR-LMHA
SAB-C167CR-LMHAIN
SABC167CRLM-HA
SABC167CRLM-HA
SABC167CRLMHAX
SP000103462
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D a t a S h e e t , V 3 . 3 , F e b . 2 0 0 5
C167CR
C167SR
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l e r
M i c r o c o n t r o l l e r s
N e v e r
s t o p
t h i n k i n g .

SAB-C167CR-LM HA+ Summary of contents

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    C167CR C167SR ...

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    ... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...

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    C167CR C167SR ...

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    C167CR, C167SR Revision History: Previous Version: Page Subjects (major changes since last revision) all The layout of several graphics and text structures has been adapted to company documentation rules, obvious typographical errors have been corrected. all The contents of this ...

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    Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    Single-Chip Microcontroller C166 Family 1 Summary of Features • High Performance 16-bit CPU with 4-Stage Pipeline – 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock – 400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 ...

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    Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis • Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards • On-Chip ...

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    ... SAK-C167SR-LM SAB-C167SR-LM SAK-C167SR-L33M SAB-C167SR-L33M SAK-C167CR-LM SAF-C167CR-LM SAB-C167CR-LM SAK-C167CR-L33M SAB-C167CR-L33M SAK-C167CR-4RM SAB-C167CR-4RM SAK-C167CR-4R33M SAB-C167CR-4R33M SAK-C167CR-16RM SAK-C167CR-16R33M 128 Kbytes SAK-C167CR-LE 1) This Data Sheet is valid for devices manufactured in 0.5 µm technology, i.e. devices starting with and including design step GA(-T)6. Data Sheet Program XRAM Size ROM Size – ...

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    General Device Information 2.1 Introduction The C167CR derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 16.5 million instructions per second) with high peripheral functionality ...

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    Pin Configuration and Definition for P-MQFP-144-8 The pins of the C167CR are described in detail in functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. Note: The P-BGA-176-2 ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 Symbol Pin Input No. Outp P6.6 7 I/O P6 ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin Input No. Outp P7.4 23 I/O P7.5 24 I/O P7.6 25 I/O P7.7 26 I/O P5 ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin Input No. Outp P2.0 47 I/O P2.1 48 I/O P2.2 49 I/O P2.3 50 I/O P2.4 51 I/O P2.5 52 I/O P2.6 53 I/O P2.7 54 I/O P2.8 ...

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    ... CLKOUT System Clock Output (= CPU Clock) Oscillator Watchdog Enable. This input enables the oscillator watchdog when high or disables it when low e.g. for testing purposes. An internal pull-up device holds this input high if nothing is driving it. For normal operation pin OWE should be high or not connected ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin Input No. Outp P4.7 92 ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin Input No. Outp. PORT0 IO P0L.0-7 100- 107 P0H.0-7 108, 111- 117 PORT1 IO P1L.0-7 118- 125 P1H.0-7 128- 135 P1H.4 132 I P1H.5 133 I P1H.6 134 I P1H.7 ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin Input No. Outp. RSTIN 140 I/O RST 141 O OUT NMI 142 – AREF V 38 – AGND Data Sheet Function Reset Input with Schmitt-Trigger characteristics. A ...

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    Table 2 Pin Definitions and Functions P-MQFP-144-8 (cont’d) Symbol Pin Input No. Outp. V 17, 46, – DD 56, 72, 82, 93, 109, 126, 136, 144 V 18, 45, – SS 55, 71, 83, 94, 110, 127, 139, 143 Note: ...

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    Pin Configuration and Definition for P-BGA-176-2 1) The pins of the C167CR are described in detail in functions. Figure 3 summarizes all pins in a condensed way, showing their location on the bottom of the package. Note: The P-MQFP-144-8 ...

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    Table 3 Pin Definitions and Functions P-BGA-176-2 Symbol Pin Input Num. Outp P5.8 B3 ...

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    Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Input Num. Outp P8.0 B10 I/O P8.1 A10 I/O P8.2 D9 I/O P8.3 C9 I/O P8.4 B9 I/O P8.5 A9 I/O P8.6 D8 I/O P8.7 C8 I/O P6 ...

  • Page 22

    Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Input Num. Outp. XTAL2 D13 O XTAL1 C13 I RST D12 O OUT RSTIN E11 I/O Data Sheet Function XTAL2: Output of the oscillator amplifier circuit. XTAL1: Input to the ...

  • Page 23

    Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Input Num. Outp. PORT1 IO P1L.0-7 K13, K14, J13, J14, H11, H12, H13, G11 P1H.0-3 G13, F11, F12, G14 P1H.4 F13 I P1H.5 F14 I P1H.6 E14 I P1H.7 E13 ...

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    Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Input Num. Outp WR WRL READY P9 I ALE P10 ...

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    ... N5 O Data Sheet Function Oscillator Watchdog Enable. This input enables the oscillator watchdog when high or disables it when low e.g. for testing purposes. An internal pull-up device holds this input high if nothing is driving it. For normal operation pin OWE should be high or not connected. In order to drive pin OWE low draw a current of at least 200 µ ...

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    Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Input Num. Outp P2.0 F3 I/O P2.1 F2 I/O P2.2 F4 I/O P2.3 G4 I/O P2.4 G3 I/O P2.5 G2 I/O P2.6 G1 I/O P2.7 H1 I/O P2.8 ...

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    Table 3 Pin Definitions and Functions P-BGA-176-2 (cont’d) Symbol Pin Input Num. Outp. V B8, – DD C12, D14, F1, H3, H14, K4, M5, M12 A8, – SS D11, E1, E12, G12, H2, L3, L5, L11, M8 Note: ...

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    Functional Description The architecture of the C167CR combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum ...

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    ... Kbytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. ...

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    External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four ...

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    ... Note: When the on-chip CAN Module used the segment address output on Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate function of the CAN interface pins. CS lines can be used to increase the total amount of addressable external memory. Data Sheet Functional Description ...

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    Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a ...

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    The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...

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    Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C167CR is capable of reacting very fast to the occurrence of non-deterministic events. The architecture ...

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    Table 4 C167CR Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...

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    Table 4 C167CR Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...

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    The C167CR also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...

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    Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as ...

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    Table 6 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only ...

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    CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs CCxIO CPU GPT2 Timer T6 Over/Underflow ...

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    General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, ...

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    T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 7 Block Diagram of GPT1 With its maximum resolution of ...

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    The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. T5EUD CPU T5IN ...

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    ... In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via register P5DIDIS (Port 5 Digital Input Disable). Data Sheet Functional Description ...

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    Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible ...

  • Page 46

    ... The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows ...

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    ... Parallel Ports The C167CR provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...

  • Page 48

    ... Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled via hardware by (externally) pulling low pin OWE (internal pull-up provides high level if not connected). In this case (OWE = ‘0’) the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler ...

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    ... BAND, BOR, AND/OR/XOR direct bit with direct bit BXOR BCMP Compare direct bit to direct bit BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 ...

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    Table 7 Instruction Set Summary (cont’d) Mnemonic Description PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR ROL / ROR Rotate left/right direct ...

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    ... Table 7 Instruction Set Summary (cont’d) Mnemonic Description DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence EXTS(R) Begin EXTended Segment (and Register) sequence NOP Null operation ...

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    ... The following table lists all SFRs which are implemented in the C167CR in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “ ...

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    Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address C1IR EF02 H C1LGML EF0A H C1LMLM EF0E H C1UAR EFn2 H C1UGML EF08 H C1UMLM EF0C H CAPREL FE4A H CC0 FE80 H CC0IC b FF78 H CC1 ...

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    Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address CC19IC b F166 H CC1IC b FF7A H CC2 FE84 H CC20 FE68 H CC20IC b F168 H CC21 FE6A H CC21IC b F16A H CC22 FE6C H CC22IC ...

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    Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address CC4 FE88 H CC4IC b FF80 H CC5 FE8A H CC5IC b FF82 H CC6 FE8C H CC6IC b FF84 H CC7 FE8E H CC7IC b FF86 H CC8 ...

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    ... H 82 Port 1 Low Reg. (Lower half of PORT1 Port 2 Register H E2 Port 3 Register H E4 Port 4 Register (8 bits Port 5 Register (read only Port 5 Digital Input Disable Register H E6 Port 6 Register (8 bits Port 7 Register (8 bits Port 8 Register (8 bits C167CR C167SR Functional Description Reset Value ...

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    Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address PECC0 FEC0 H PECC1 FEC2 H PECC2 FEC4 H PECC3 FEC6 H PECC4 FEC8 H PECC5 FECA H PECC6 FECC H PECC7 FECE H PICON b F1C4 H PDCR ...

  • Page 58

    Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address S0EIC b FF70 H S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C H S0TBUF FEB0 H S0TIC b FF6C H SP FE12 H SSCBR F0B4 H SSCCON ...

  • Page 59

    Table 8 C167CR Registers, Ordered by Name (cont’d) Name Physical Address T2IC b FF60 H T3 FE42 H T3CON b FF42 H T3IC b FF62 H T4 FE44 H T4CON b FF44 H T4IC b FF64 H T5 FE46 H ...

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    Electrical Parameters 4.1 General Parameters Table 9 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ( ...

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    ... Power Down mode V Reference voltage 2)3) mA Per pin Pin drivers in fast edge mode (PDCR.BIPEC = ‘0’) pF Pin drivers in reduced edge mode (PDCR.BIPEC = ‘1’) pF Pin drivers in fast edge mode MHz CPUmax °C SAB-C167CR … °C SAF-C167CR … °C SAK-C167CR … V3.3, 2005-02 3) ...

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    Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CR and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...

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    Table 11 DC Characteristics (Operating Conditions apply) Parameter 3) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 3) Output high voltage (all other outputs) Input leakage current (Port 5) Input leakage current 4) (all other) ...

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    This specification is valid during Reset and during Adapt-mode. 10) Not subject to production test - verified by design/characterization. Table 12 Power Consumption C167CR (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply ...

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    I [mA] 140 120 100 Figure 9 Supply/Idle Current as a Function of Operating Frequency Data Sheet C167CR C167SR Electrical Parameters I DDmax I DDtyp I IDmax I IDtyp 40 f [MHz] ...

  • Page 66

    Analog/Digital Converter Parameters Table 13 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage ...

  • Page 67

    During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final voltage level within After the end of the sample time result. t Values for the sample time S ...

  • Page 68

    AC Parameters 4.4.1 Definition of Internal Timing The internal operation of the C167CR is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of ...

  • Page 69

    PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5). Table 15 associates the combinations of these three bits with the respective clock generation mode. Table 15 C167CR Clock Generation Modes CLKCFG CPU Frequency ...

  • Page 70

    The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As ...

  • Page 71

    ... Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock ...

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    External Clock Drive XTAL1 Table 16 External Clock Drive Characteristics (Operating Conditions apply) Parameter Symbol t Oscillator period OSC 2) t High time Low time Rise time Fall time 4 ...

  • Page 73

    Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at Figure 13 Input Output Waveforms V + 0.1 ...

  • Page 74

    External Bus Timing Table 17 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter. For a single CLKOUT ...

  • Page 75

    Table 19 External Bus Cycle Timing (Operating Conditions apply) Parameter Output delay from CLKOUT falling edge Valid for: address, BHE, early CS, write data out, ALE Output delay from CLKOUT rising edge Valid for: latched CS, ALE low Output delay ...

  • Page 76

    General Notes for the Following Timing Figures These standard notes apply to all subsequent timing figures. Additional individual notes are placed at the respective figure. 1. The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay ...

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    CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A0 BHE, CSxE WRL, WRH, WR, WrCS D15-D0 Figure 16 Demultiplexed Bus, Write Access Data Sheet Normal ALE Cycle Extended ALE Cycle ...

  • Page 78

    CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A0, BHE, CSxE RD, RdCS D15-D0 Figure 17 Demultiplexed Bus, Read Access Data Sheet Normal ALE Cycle Extended ALE Cycle ...

  • Page 79

    CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A16 BHE, CSxE WRL, WRH, WR, WrCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 18 Multiplexed Bus, Write Access Data Sheet Normal ALE Cycle tc 11 ...

  • Page 80

    CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A16 BHE, CSxE RD, RdCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 19 Multiplexed Bus, Read Access Data Sheet Normal ALE Cycle ...

  • Page 81

    ... If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates and the ALE mode of the next following cycle ...

  • Page 82

    Running Cycle CLKOUT D15-D0 D15-D0 Command (RD, WR) Synchronous READY tc 25 Asynchronous 5) READY Figure 20 READY Timings Data Sheet Data OUT ...

  • Page 83

    External Bus Arbitration Table 21 Bus Arbitration Timing (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay 1) CSx release CSx drive 1) Other signals release 1) Other signals ...

  • Page 84

    CLKOUT tc 28 HOLD HLDA BREQ CS Other Signals Figure 21 External Bus Arbitration, Releasing the Bus Notes 1. The C167CR will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ ...

  • Page 85

    CLKOUT HOLD HLDA BREQ CS Other Signals Figure 22 External Bus Arbitration, Regaining the Bus Notes 4. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by ...

  • Page 86

    External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed (during hold states external master like an asynchronous SRAM. Table 22 XRAM Access Timing (Operating Conditions apply) Parameter Address setup time ...

  • Page 87

    Package Outlines 0.65 144x 0.3 ±0.08 0.12 A 0.65 = 22.75 31 144 45˚ Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side ...

  • Page 88

    Figure 25 P-BGA-176-2 (Plastic Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet A14 176x +0.14 ...

  • Page 89

    ... Published by Infineon Technologies AG ...