SAB-C167CR-LM HA+ Infineon Technologies, SAB-C167CR-LM HA+ Datasheet - Page 74

• Manufacturer Part Number: SAB-C167CR-LM HA+
• Description: IC MCU 16BIT MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C167CR-LM HA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 16 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 16
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B167CRLMHAZNP; B167CRLMHAZXP; SAB-C167CR-LMHA; SAB-C167CR-LMHA+; SAB-C167CR-LMHA; SAB-C167CR-LMHAIN; SABC167CRLM-HA; SABC167CRLM-HA; SABC167CRLMHAX; SP000103462

4.4.4
Table 17
Parameter
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
1) The CLKOUT cycle time is influenced by the PLL jitter.
Figure 15
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 18
Bus Cycle Type
Demultiplexed bus cycle
with normal ALE
Demultiplexed bus cycle
with extended ALE
Multiplexed bus cycle with
normal ALE
Multiplexed bus cycle with
extended ALE
Data Sheet
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for
For longer periods the relative deviation decreases (see PLL deviation formula).
CLKOUT
External Bus Timing
CLKOUT Reference Signal
CLKOUT Signal Timing
Variable Memory Cycles
tc
5
Bus Cycle Duration
4 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
8 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
tc
6
tc
72
7
Symbol
tc
tc
tc
tc
tc
5
6
7
8
9
Unit
TCL
TCL
TCL
TCL
CC
CC
CC
CC
CC
tc
8
25/33 MHz, 0 Waitstates
80 ns/60.6 ns
120 ns/90.9 ns
120 ns/90.9 ns
160 ns/121.2 ns
Min.
8
6
–
–
Electrical Parameters
tc
9
Limits
30
1)
Max.
–
–
4
4
f
V3.3, 2005-02
CPU
C167CR
C167SR
> 25 MHz).
MCT04415
Unit
ns
ns
ns
ns
ns