T89C5115-TISUM Atmel, T89C5115-TISUM Datasheet
T89C5115-TISUM
Specifications of T89C5115-TISUM
Related parts for T89C5115-TISUM
T89C5115-TISUM Summary of contents
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... Idle Mode – Power-down Mode • Power Supply: 3 Volts to 5.5 Volts • Temperature Range: Industrial (-40° to +85°C) • Packages: SOIC28, SOIC24, PLCC28, VQFP32 Low Pin Count 8-bit Microcontroller with A/D Converter and 16 KBytes Flash Memory T89C5115 AT89C5115 Rev. 4128G–8051–02/08 ...
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... ISP capability or with software. The programming voltage is internally gener- ated from the standard VCC pin. The T89C5115 retains all features of the 80C52 with 256 bytes of internal RAM source 4-level interrupt controller and three timer/counters. In addition, the T89C5115 has a 10-bit A/D converter, a 2-KB Boot Flash memory, 2-KB EEPROM for data, a Pro- grammable Counter Array, an XRAM of 256 bytes, a Hardware WatchDog Timer and a more versatile serial channel that facilitates multiprocessor communication (EUART) ...
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Pin Configurations 4128G–8051–02/08 VAREF VAGND 2 26 VAVCC 3 25 P4 P3.7 SO28 P3.5/T1 P3.4/ P3.3/INT1 P3.2/INT0 17 ...
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... AT89C5115 P3.6 QFP- P3.5/ P3.4/ P3.3/INT1 8 P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 NC RESET 4128G–8051–02/08 ...
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... As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. In the T89C5115 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. 4128G–8051–02/08 , See section ’ ...
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... Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2 O XTAL2: Output from the inverting oscillator amplifier. AT89C5115 6 , See section ’Electrical Characteristic’) IL 4128G–8051–02/08 ...
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I/O Configurations Port Structure 4128G–8051–02/08 Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A CPU ...
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... Read-Modify-Write Instructions Quasi Bi-directional Port Operation AT89C5115 8 Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called ’Read- Modify-Write’ instructions. Below is a complete list of these special instructions (See Table 1) ...
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This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. Note: During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the pin. Figure 2. Internal ...
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... TL1 8Bh byte Timer/Counter 2 High TH2 CDh byte Timer/Counter 2 Low TL2 CCh byte Timer/Counter 0 and TCON 88h 1 control Timer/Counter 0 and TMOD 89h 1 Modes AT89C5115 10 Tables 3 through Table 11 show the Special Function Registers (SFRs) of the T89C5115 TF1 TR1 TF0 GATE1 C/T1# M11 ...
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Table 4. Timers SFRs (Continued) Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WatchDog Timer WDTRST A6h Reset WatchDog Timer WDTPRG ...
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... ADDL F4h ADC Data Low byte Table 9. Other SFRs Mnemonic Add Name PCON 87h Power Control AUXR1 A2h Auxiliary Register 1 CKCON 8Fh Clock Control FCON D1h Flash Control EECON D2h EEPROM Contol AT89C5115 CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 7 6 ...
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Table 10. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx xx0x 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx xx0x 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 0xxx x000 PSW FCON D0h 0000 ...
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... Clock Description AT89C5115 14 The T89C5115 core needs only 6 clock periods per machine cycle. This feature, called “X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • ...
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Figure 3. Clock CPU Generation Diagram Hardware byte XTAL1 XTAL2 PD PCON.1 ÷ CKCON.0 4128G–8051–02/08 X2B PCON.0 On RESET IDL X2 CKCON.0 0 ÷ ÷ 2 ÷ ÷ ÷ 1 ...
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... For example, a free run- ning timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate. AT89C5115 16 (1) ...
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Register 4128G–8051–02/08 Table 11. CKCON Register CKCON (S:8Fh) Clock Control Register WDX2 PCAX2 Bit Bit Number Mnemonic Description Reserved not set this bit. Watchdog Clock 6 WDX2 Clear to select 6 clock periods ...
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... At Power-up (cold reset) AT89C5115 18 Two power reduction modes are implemented in the T89C5115: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 Mode detailed in Section “Clock”. ...
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During a Normal Operation (Warm Reset) Watchdog Reset 4128G–8051–02/08 Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor oscrst/vddrst 1ms 5ms 2.7µF 20ms 10µF Note: These values assume VDD starts from 0v to the nominal value. If the time ...
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... Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 12. To enter Idle mode, set the IDL bit in PCON register (See Table 15). The T89C5115 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
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... Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C5115 and vectors the CPU to address 0000h. Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed ...
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... AT89C5115 22 Table 14. Pin Conditions in Special Operating Modes Down(inter Mode Port 1 Port 2 Port 3 Reset High High Idle (internal Data Data code) Idle (external Data Data code) Power- Data Data nal code) Power- Down Data Data (external code) Port 4 High High Data Data ...
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Registers 4128G–8051–02/08 Table 15. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...
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... Data Memory Internal Space Lower 128 Bytes RAM AT89C5115 24 The T89C5115 provides data memory access in two different spaces: The internal space mapped in three separate segments: • The lower 128 Bytes RAM segment. • The upper 128 Bytes RAM segment. • The expanded 256 Bytes RAM segment (XRAM). ...
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Upper 128 Bytes RAM Expanded RAM 4128G–8051–02/08 Figure 10. Lower 128 Bytes Internal RAM Organization 30h 20h 18h 10h 08h 00h The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. The ...
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... Application AT89C5115 26 The T89C5115 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are Seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (See Figure 18) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (See Figure 11) ...
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Registers 4128G–8051–02/08 Table 17. PSW Register PSW (S:D0h) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 AC ...
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... AT89C5115 28 Table 18. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register ENBOOT Bit Bit Number Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. Enable Boot Flash (1) 5 ENBOOT Set this bit to map the boot Flash between F800h -FFFFh Clear this bit to disable boot Flash ...
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EEPROM Data Memory Write Data in the Column Latches Programming Read Data 4128G–8051–02/08 The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in ...
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... Examples AT89C5115 30 ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: ; Save and clear EA MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ...
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Registers 4128G–8051–02/08 Table 19. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the ...
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... Column Latches (128 Bytes) AT89C5115 32 The T89C5115 implement 16K Bytes of on-chip program/code memory. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V age ...
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FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Byte Column Latches Cross Flash Memory Access Description 4128G–8051–02/08 The Flash memory is made blocks (See Figure 13): 1. The memory array (user space) 16K Bytes 2. ...
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... Overview of FM0 Operations Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column Launching Programming AT89C5115 34 The CPU interfaces the Flash memory through the FCON register and AUXR1 register. These registers are used to: • Map the memory spaces in the adressable space • ...
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Status of the Flash Memory Selecting FM1 Loading the Column Latches 4128G–8051–02/08 The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. The bit ENBOOT in AUXR1 register ...
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... Programming the Flash Spaces User Extra Row AT89C5115 36 Figure 14. Column Latches Loading Procedure Note: 1. The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is used to program the User space and is summarized in Figure 15: • ...
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Hardware Security Byte 4128G–8051–02/08 Figure 15. Flash and Extra row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 16: • Set FPS and map Hardware byte (FCON = 0x0C) • Save then ...
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... Reading the Flash Spaces User Extra Row Hardware Security Byte AT89C5115 38 Figure 16. Hardware Programming Procedure Flash Spaces Programming Save & Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A End Loading Restore IT The following procedure is used to read the User space: • ...
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Flash Protection from Parallel Programming Preventing Flash Corruption 4128G–8051–02/08 Figure 17. Reading Procedure Note for the Hardware Security Byte. The three lock bits in Hardware Security Byte (See ’In-System Programming’ section) are programmed according to Table 23 ...
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... Registers AT89C5115 40 Table 24. FCON Register FCON Register FCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits FPL3:0 Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (See Table 22.) Flash Map Program Space 3 FPS Set to map the column latch space in the data memory space ...
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4128G–8051–02/08 41 ...
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... Table 25. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write Note: 1. RWW: Read While Write AT89C5115 42 Space addressable in read and write are: • RAM • ERAM (Expanded RAM access by movx) • EEPROM DATA • FM0 ( user flash ) • ...
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Sharing Instructions 4128G–8051–02/08 Table 26. Instructions shared EEPROM Action RAM ERAM Read MOV MOVX Write MOV MOVX Note using Column Latch Table 27. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register 0 ...
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... For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh 2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh AT89C5115 44 FPS ENBOOT ...
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... With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C5115 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • ...
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... Flash pages. All calls are made by functions. All these APIs are described in detail in the following documents on the Atmel web site. – Datasheet Bootloader UART T89C5115. bit ENBOOT in AUXR1 Register Is Initialized with BLJB Inverted. Example, if BLJB=0, ENBOOT ...
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... During the first programming, the user can define a configuration on Port1 that will be recognized by the chip as the hardware conditions during a Reset. If this condition is met, the chip will start executing the bootloader at the end of the Reset. See a detailed description in the applicable Document. – – Datasheet Bootloader UART T89C5115. Default Value Address 58h 30h D7h ...
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... Hardware Security Byte AT89C5115 48 Table 31. Hardware Security byte X2B BLJB - Bit Bit Number Mnemonic Description X2 bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 Mode. Boot Loader Jump bit 6 BLJB - 1: To start the user’s application on next RESET (@0000h) located in FM0 start the boot loader(@F800h) located in FM1 ...
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... RXD Framing Error Detection 4128G–8051–02/08 The T89C5115 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
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... Automatic Address Recognition Given Address AT89C5115 50 Figure 22. UART Timing in Mode 1 RXD D0 D1 Start bit RI SMOD0 = x FE SMOD0 = 1 Figure 23. UART Timing in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set) ...
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Broadcast Address 4128G–8051–02/08 Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN ...
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... Registers AT89C5115 52 Table 32. SCON Register SCON (S:98h) Serial Control Register FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0 = Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Serial port Mode bit 0 (SMOD0 = 0) SM0 Refer to SM1 for serial port mode selection ...
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Table 33. SADEN Register SADEN (S:B9h) Slave Address Mask Register Bit Bit Number Mnemonic Description Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 34. SADDR Register ...
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... AT89C5115 54 Table 36. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 6 SMOD0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. ...
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... Operations Timer 0 4128G–8051–02/08 The T89C5115 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. ...
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... GATEx TMOD Reg Mode 2 (8-bit Timer with Auto- Reload) AT89C5115 56 Mode 0 configures Timer 13-bit Timer which is set 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (See Figure 24). The upper three bits of TL0 register are indeterminate and should be ignored ...
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Figure 26. Timer/Counter x ( Mode 2 See section “Clock” FTx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx# GATEx TMOD Reg Mode 3 (Two 8-bit Timers) Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit ...
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... Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt AT89C5115 58 • For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. ...
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Registers 4128G–8051–02/08 Table 37. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by hardware ...
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... AT89C5115 60 Table 38. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. ...
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Table 40. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 41. TH1 Register TH1 (S:8Dh) Timer 1 High ...
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... T2 AT89C5115 62 The T89C5115 Timer 2 is compatible with Timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eightbit timer registers, TH2 and TL2 that are cascade-connected controlled by T2CON register (See Table 44) and T2MOD register (See Table 45). Timer 2 operation is similar to Timer 0 and Timer 1 ...
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Programmable Clock- Output Figure 30. Clock-Out Mode FT2 CLOCK T2 T2EX 4128G–8051–02/08 In clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (Figure 30). The input clock increments TL2 at frequency f repeatedly counts to overflow from ...
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... Registers AT89C5115 64 Table 43. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 Must be cleared by software. Set by hardware on Timer 2 overflow. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
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Table 44. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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... AT89C5115 66 Table 46. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description Low Byte of Timer 2 Reset Value = 0000 0000b Not bit addressable Table 47. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register Bit Bit Number Mnemonic Description High Byte of Timer 2 Reload/Capture. ...
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... Fwd Clock WDTPRG - 4128G–8051–02/08 T89C5115 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Timeout ranging from 16ms mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis- ter ...
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... Watchdog Programming AT89C5115 68 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 49. Machine Cycle Count compute WD Timeout, the following formula is applied: ---------------------------------------------------------------------------- - FTime Out – = WDX2 6 2 × Note: Svalue represents the decimal value of (S2 S1 S0) Find Hereafter computed Timeout values for f Table 50 ...
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... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C5115 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
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... AT89C5115 70 Table 52. WDTRST Register WDTRST (S:A6h Write Only) – Watchdog Timer Enable register Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences. ...
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Programmable Counter Array (PCA) PCA Timer 4128G–8051–02/08 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves ...
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... Figure 32. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle AT89C5115 72 CIDL CPS1 CPS0 CF CR The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. • The ECF bit which when set causes an interrupt and the PCA overflow flag CF in CCON register to be set when the PCA timer overflows ...
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PCA Modules 4128G–8051–02/08 Each one of the two compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • 16-bit Capture, negative-edge triggered • 16-bit Capture, both positive and negative-edge triggered • 16-bit Software Timer • ...
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... Module 1 ECF CMOD.0 PCA Capture Mode Figure 34. PCA Capture Mode CEXn AT89C5115 ECCFn CCAPMn.0 To use one of the PCA modules in capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’ ...
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Software Timer Mode Figure 35. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to CCAPnH 4128G–8051–02/08 The PCA modules can be used as software ...
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... Enable Pulse Width Modulator Mode AT89C5115 76 In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set ...
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Figure 37. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) 4128G–8051–02/08 CCAPnH CCAPnL “0” CL < CCAPnL 8-bit Comparator CL >= CCAPnL “1” ECOMn PWMn CCAPMn.6 CCAPMn.1 CEX 77 ...
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... PCA Registers AT89C5115 78 Table 53. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL - - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. Reserved ...
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Table 54. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Number Bit Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This 7 CF generates a ...
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... AT89C5115 80 Table 55. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 Bit Number Bit Mnemonic Description 7:0 CCAPnH 7:0 High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Table 56. CCAPnL Registers CCAP0L (S:EAh) CCAP1L (S:EBh) PCA Low Byte Compare/Capture Module n Register (n=0 ...
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Table 57. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Number Bit Mnemonic Description Reserved 7 - The Value read from this bit is indeterminate. Do not ...
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... AT89C5115 82 Table 58. CH Register CH (S:F9h) PCA Counter Register High value Bit Number Bit Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 59. CL Register CL (S:E9h) PCA counter Register Low value Bit Number Bit Mnemonic Description 7:0 CL0 7:0 ...
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... ADC Port1 I/O Functions VAREF 4128G–8051–02/08 This section describes the on-chip 10-bit analog-to-digital converter of the T89C5115. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC chan- nels as ADC input voltage (ADCIN) ...
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... Note: Tsetup min, see the AC Parameter for A/D conversion. Tconv = 11 clock ADC = 1sample and hold + 10-bit conversion The user must ensure that Tsetup time between setting ADEN and the start of the first conversion. ADC Converter Operation AT89C5115 84 ADCON.5 ADCON.3 ADEN ADSST ...
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Voltage Conversion Clock Selection Figure 40. A/D Converter Clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode IT ADC management 4128G–8051–02/08 The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 60. ...
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... Routine Examples AT89C5115 86 Figure 41. ADC interrupt structure ADEOC ADCON.2 1. Configure P1.2 and P1.3 in ADC channels // configure channel P1.2 and P1.3 for ADC ADCF = 0Ch // Enable the ADC ADCON = 20h 2. Start a standard conversion // The variable ’channel’ contains the channel to convert // The variable ’value_converted’ unsigned int // Clear the field SCH[2:0] ADCON & ...
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Registers 4128G–8051–02/08 Table 61. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 0:7 Set to use P1.x as ADC input. Clear to ...
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... AT89C5115 88 Table 63. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler Fadc = Fcpuclock/(4*PRS mode 4-0 PRS4:0 Fadc=Fcpuclock/(2*PRS mode Reset Value = XXX0 0000b Table 64 ...
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... UART RxD Timer 2 ADC AIN1:0 4128G–8051–02/08 The T89C5115 has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCAand an ADC. These interrupts are shown below. EX0 IEN0.0 ET0 IEN0 ...
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... AT89C5115 90 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers ...
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Registers 4128G–8051–02/08 Figure 43. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, ...
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... AT89C5115 92 Figure 44. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 68. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority ...
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... AT89C5115 94 Table 69. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 70. IPH0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...
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... AT89C5115 96 Table 71. IPH1 Register IPH1 (S:F7h) Interrupt high priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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Electrical Characteristics Absolute Maximum Ratings industrial ....................................................... -40°C to 85°C Storage Temperature ................................... -65° 150°C Voltage on V from V .....................................-0. Voltage on Any Pin from V .....................-0. ...
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... V + 0.5V 0.5V; XTAL2 N.C.; RST = 45.). 7. ICC_FLASH_WRITE operating current while a Flash block write is on going. AT89C5115 98 must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL (See Figure 46.). would be slightly higher if a crystal oscillator used (See Figure ...
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DC Parameters for A/D Converter 4128G–8051–02/08 Figure 47. I Test Condition, Power-down Mode VaVcc RST (NC) XTAL2 XTAL1 VAGND V SS Figure 48. Clock Signal Waveform for I V -0.5V CC 0.45V T ...
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... AC Parameters Serial Port Timing - Shift Register Mode AT89C5115 100 Table 74. Symbol Description ( MHz) Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 75. AC Parameters for a Fix Clock ( MHz) Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 76. AC Parameters for a Variable Clock Symbol Type T Min ...
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Shift Register Timing Waveforms INSTRUCTION CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms 4128G–8051–02/ XLXL ...
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... Clock Waveforms Flash/EEPROM Memory A/D Converter AT89C5115 102 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V occurs ≥ ± 20mA Valid in normal clock mode Mode XTAL2 must be changed to XTAL2/2. ...
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... Ordering Information Table 80. Possible Order Entries Memory Size Part-Number T89C5115-SISIM T89C5115-TISIM T89C5115-RATIM AT89C5115-SISUM 16K AT89C5115-TISUM 16K AT89C5115-RATUM 16K 4128G–8051–02/08 Supply Temperature Voltage Range Frequency OBSOLETE 5V Industrial & Green 5V Industrial & Green 5V Industrial & Green Max Package Packing 40 MHz PLCC28 ...
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... Package Drawings VQFP32 AT89C5115 104 4128G–8051–02/08 ...
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PLCC28 4128G–8051–02/08 105 ...
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... SOIC24 AT89C5115 106 4128G–8051–02/08 ...
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SOIC28 4128G–8051–02/08 107 ...
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... Datasheet Revision History for T89C5115 Changes from 4128A- 01/03 to 4128B-06/03 Changes from 4128B- 06/03 to 4128C-12/03 Changes from 4128C - 12/03 to 4128D - 01/05 Changes from 4128D - 01/05 to 4128E - 10/05 Changes from 4128E - 10/05 to 4182F - 06/05 Changes from 4182F - 06/05 to 4182G - 01/08 AT89C5115 108 1 ...
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Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 2 Pin Configurations ................................................................................ 3 Pin Description...................................................................................... 5 I/O Configurations ................................................................................................. 7 Port Structure ....................................................................................................... 7 Read-Modify-Write Instructions ............................................................................ 8 Quasi Bi-directional Port Operation ...................................................................... 8 SFR Mapping ....................................................................................... 10 Clock ...
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Program/Code Memory ...................................................................... 32 Operation Cross Memory Access ..................................................... 42 Sharing Instructions ........................................................................... 43 In-System Programming (ISP) ........................................................... 45 Serial I/O Port ...................................................................................... 49 ..................................................................................Timers/Counters 55 Timer 2 ................................................................................................. 62 Watchdog Timer .................................................................................. 67 Watchdog Timer During Power-down Mode and ...
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... Absolute Maximum Ratings* .............................................................................. 97 DC Parameters for A/D Converter...................................................................... 99 AC Parameters ................................................................................................. 100 Ordering Information ........................................................................ 103 Package Drawings ............................................................................ 104 VQFP32............................................................................................................ 104 PLCC28 ............................................................................................................ 105 SOIC24............................................................................................................. 106 SOIC28............................................................................................................. 107 Datasheet Revision History for T89C5115...................................... 108 Changes from 4128A-01/03 to 4128B-06/03.................................................... 108 Changes from 4128B-06/03 to 4128C-12/03 ................................................... 108 iii ...
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... AT89C5115 iv Changes from 4128C -12/03 to 4128D - 01/05................................................. 108 Changes from 4128D - 01/05 to 4128E - 10/05................................................ 108 Changes from 4128E - 10/05 to 4182F - 06/05 ................................................ 108 Changes from 4182F - 06/05 to 4182G - 01/08................................................ 108 4128G–8051–02/08 ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...