PIC24HJ256GP610-I/PT Microchip Technology, PIC24HJ256GP610-I/PT Datasheet
PIC24HJ256GP610-I/PT
Specifications of PIC24HJ256GP610-I/PT
Available stocks
Related parts for PIC24HJ256GP610-I/PT
PIC24HJ256GP610-I/PT Summary of contents
Page 1
... Microchip Technology Inc. PIC24H Family Data Sheet High-Performance, 16-bit Microcontrollers Preliminary DS70175C ...
Page 2
... PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Output pins can drive from 3.0V to 3.6V • All digital input pins are 5V tolerant • sink on all I/O pins © 2006 Microchip Technology Inc. On-Chip Flash and SRAM • Flash program memory 256 Kbytes • Data SRAM Kbytes (includes 2 Kbytes ...
Page 4
... Fully static design • 3.3V (±10%) operating voltage • Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. Preliminary © 2006 Microchip Technology Inc. ...
Page 5
... PIC24HJ128GP510 100 128 PIC24HJ128GP306 64 128 PIC24HJ128GP310 100 128 PIC24HJ256GP206 64 256 PIC24HJ256GP210 100 256 PIC24HJ256GP610 100 256 Note 1: RAM size is inclusive of 2 Kbytes DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions. © 2006 Microchip Technology Inc ADC, ...
Page 6
... PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins. DS70175C-page 4 48 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 47 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 PIC24HJ64GP206 OSC2/CLKO/RC15 PIC24HJ128GP206 39 OSC1/CLKIN/RC12 PIC24HJ256GP206 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 Preliminary SS DD © 2006 Microchip Technology Inc. ...
Page 7
... RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2006 Microchip Technology Inc. 48 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 47 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 PIC24HJ128GP306 OSC2/CLKO/RC15 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 Preliminary PIC24H SS DD ...
Page 8
... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70175C-page 6 48 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 47 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 46 OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/INT1/RD8 41 V PIC24HJ64GP506 40 OSC2/CLKO/RC15 PIC24HJ128GP506 39 OSC1/CLKIN/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 Preliminary SS DD © 2006 Microchip Technology Inc. ...
Page 9
... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2006 Microchip Technology Inc. PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210 Preliminary PIC24H PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 ...
Page 10
... AN3/CN5/RB3 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 25 PGD3/EMUD3/AN0/CN2/RB0 DS70175C-page 8 PIC24HJ64GP510 PIC24HJ128GP510 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 IC2/RD9 69 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 58 SCL2/RA2 57 SCL1/RG2 SDA1/RG3 56 SCK1/INT0/RF6 55 54 SDI1/RF7 SDO1/RF8 53 52 U1RX/RF2 51 U1TX/RF3 © 2006 Microchip Technology Inc. ...
Page 11
... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2006 Microchip Technology Inc. PIC24HJ256GP610 Preliminary PIC24H PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 73 72 OC1/RD0 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 SCL2/RA2 ...
Page 12
... Electrical Characteristics .......................................................................................................................................................... 239 24.0 Packaging Information.............................................................................................................................................................. 273 Appendix A: Revision History............................................................................................................................................................. 277 Index ................................................................................................................................................................................................. 279 The Microchip Web Site ..................................................................................................................................................................... 283 Customer Change Notification Service .............................................................................................................................................. 283 Customer Support .............................................................................................................................................................................. 283 Reader Response .............................................................................................................................................................................. 284 Product Identification System............................................................................................................................................................. 285 DS70175C-page 10 Preliminary © 2006 Microchip Technology Inc. ...
Page 13
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 11 ...
Page 14
... PIC24H NOTES: DS70175C-page 12 Preliminary © 2006 Microchip Technology Inc. ...
Page 15
... PIC24HJ128GP306 • PIC24HJ128GP310 • PIC24HJ256GP206 • PIC24HJ256GP210 • PIC24HJ256GP610 The PIC24H device family includes devices with differ- ent pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes). ...
Page 16
... Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR ECAN1,2 UART1,2 CN1-23 SPI1,2 I2C1,2 Preliminary PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 16 PORTF 16 PORTG © 2006 Microchip Technology Inc. ...
Page 17
... I/O ST Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2006 Microchip Technology Inc. Description Analog input channels. Positive supply for analog modules. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...
Page 18
... UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Preliminary © 2006 Microchip Technology Inc. ...
Page 19
... The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. © 2006 Microchip Technology Inc. 2.2 Special MCU Features The PIC24H features a 17-bit by 17-bit, single-cycle multiplier ...
Page 20
... DS70175C-page 18 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support Preliminary DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2006 Microchip Technology Inc. ...
Page 21
... FIGURE 2-2: PIC24H PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2006 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
Page 22
... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70175C-page 20 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2006 Microchip Technology Inc. ...
Page 23
... Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 21 ...
Page 24
... Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70175C-page 22 U-0 U-0 U-0 — — — U-0 R/C-0 R/W-0 (1) — IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) Preliminary © 2006 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit 0 ‘1’ = Bit is set ...
Page 25
... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2006 Microchip Technology Inc. 2.4.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
Page 26
... PIC24H NOTES: DS70175C-page 24 Preliminary © 2006 Microchip Technology Inc. ...
Page 27
... Reserved Device Configuration Registers Reserved DEVID (2) © 2006 Microchip Technology Inc. 3.1 Program Address Space The program address memory space of the PIC24H devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3 ...
Page 28
... Interrupt Service Routines (ISRs). A more detailed dis- cussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2006 Microchip Technology Inc. ...
Page 29
... Data byte writes only write to the corresponding side of the array or register which matches the byte address. © 2006 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...
Page 30
... Optionally Mapped into Program Memory 0xFFFF DS70175C-page 28 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8-Kbyte Near Data Space © 2006 Microchip Technology Inc. ...
Page 31
... DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various © 2006 Microchip Technology Inc. LSB Address 16 bits MSB ...
Page 32
... PIC24H DS70175C-page 30 Preliminary © 2006 Microchip Technology Inc. ...
Page 33
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 31 ...
Page 34
... PIC24H DS70175C-page 32 Preliminary © 2006 Microchip Technology Inc. ...
Page 35
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 33 ...
Page 36
... PIC24H DS70175C-page 34 Preliminary © 2006 Microchip Technology Inc. ...
Page 37
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 35 ...
Page 38
... PIC24H DS70175C-page 36 Preliminary © 2006 Microchip Technology Inc. ...
Page 39
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 37 ...
Page 40
... PIC24H DS70175C-page 38 Preliminary © 2006 Microchip Technology Inc. ...
Page 41
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 39 ...
Page 42
... PIC24H DS70175C-page 40 Preliminary © 2006 Microchip Technology Inc. ...
Page 43
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 41 ...
Page 44
... PIC24H DS70175C-page 42 Preliminary © 2006 Microchip Technology Inc. ...
Page 45
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 43 ...
Page 46
... PIC24H DS70175C-page 44 Preliminary © 2006 Microchip Technology Inc. ...
Page 47
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 45 ...
Page 48
... PIC24H DS70175C-page 46 Preliminary © 2006 Microchip Technology Inc. ...
Page 49
... Microchip Technology Inc. Preliminary PIC24H DS70175C-page 47 ...
Page 50
... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. Preliminary © 2006 Microchip Technology Inc. addressing modes are ...
Page 51
... In some instructions, the source of an oper- and or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2006 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
Page 52
... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx Preliminary © 2006 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
Page 53
... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2006 Microchip Technology Inc. Program Counter 0 23 bits ...
Page 54
... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area. Preliminary © 2006 Microchip Technology Inc. ...
Page 55
... PSVPAG is mapped into the upper half of the data memory space... © 2006 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
Page 56
... PIC24H NOTES: DS70175C-page 54 Preliminary © 2006 Microchip Technology Inc. ...
Page 57
... Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data in blocks or ‘rows’ instructions (192 bytes time, and erase pro- gram memory in blocks or ‘ ...
Page 58
... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for Preliminary © 2006 Microchip Technology Inc. ...
Page 59
... Memory page erase operation (ERASE = operation (ERASE = 0) 0001 = Memory row program operation (ERASE = operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2006 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...
Page 60
... Initialize in-page EA<15:0> pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2006 Microchip Technology Inc. ...
Page 61
... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2006 Microchip Technology Inc Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...
Page 62
... PIC24H NOTES: DS70175C-page 60 Preliminary © 2006 Microchip Technology Inc. ...
Page 63
... DD Internal Regulator Trap Conflict Illegal Opcode Uninitialized W Register © 2006 Microchip Technology Inc. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits, except for the POR bit (RCON< ...
Page 64
... DS70175C-page 62 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 65
... All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2006 Microchip Technology Inc. (1) Preliminary PIC24H DS70175C-page 63 ...
Page 66
... The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the reset signal is released. Preliminary Clearing Event POR POR POR POR PWRSAV instruction, POR POR POR — — © 2006 Microchip Technology Inc. ...
Page 67
... Reset signal is released valid clock source is not available at this time, the device automatically switches to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2006 Microchip Technology Inc. System Clock SYSRST Delay Delay T ...
Page 68
... PIC24H NOTES: DS70175C-page 66 Preliminary © 2006 Microchip Technology Inc. ...
Page 69
... PIC24H devices implement unique interrupts and 5 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2. © 2006 Microchip Technology Inc. 6.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
Page 70
... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70175C-page 68 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2006 Microchip Technology Inc. ...
Page 71
... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...
Page 72
... AIVT Address 0x000004 0x000084 0x000006 0x000086 0x000008 0x000088 0x00000A 0x00008A 0x00000C 0x00008C 0x00000E 0x00008E 0x000010 0x000090 0x000012 0x000092 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2006 Microchip Technology Inc. ...
Page 73
... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2006 Microchip Technology Inc. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
Page 74
... Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 U-0 PSV — — bit 0 ‘1’ = Bit is set © 2006 Microchip Technology Inc. ...
Page 75
... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
Page 76
... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70175C-page 74 Preliminary © 2006 Microchip Technology Inc. ...
Page 77
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 78
... Interrupt request has not occurred DS70175C-page 76 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA01IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 79
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 77 ...
Page 80
... Interrupt request has not occurred DS70175C-page 78 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IF DMA21IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 81
... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 79 ...
Page 82
... Interrupt request has not occurred DS70175C-page 80 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF R/W-0 R/W-0 R/W-0 DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 83
... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 81 ...
Page 84
... Interrupt request has not occurred DS70175C-page 82 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 T9IF T8IF MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — C2IF bit 8 R/W-0 R/W-0 SI2C2IF T7IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 85
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 86
... Interrupt request not enabled DS70175C-page 84 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 87
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 85 ...
Page 88
... Interrupt request not enabled DS70175C-page 86 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 89
... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 87 ...
Page 90
... Interrupt request has not occurred DS70175C-page 88 R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE R/W-0 R/W-0 R/W-0 DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC5IE IC6IE bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 91
... Interrupt request has not occurred bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 89 ...
Page 92
... Interrupt request has not occurred DS70175C-page 90 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 T9IE T8IE MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — C2IE bit 8 R/W-0 R/W-0 SI2C2IE T7IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 93
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 94
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 92 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 95
... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 96
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 94 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 98
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 96 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 100
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 98 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 102
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 100 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 104
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 102 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 IC6IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 105
... Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
Page 106
... Interrupt is priority 1 000 = Interrupt source is disabled DS70175C-page 104 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 T7IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 108
... Interrupt source is disabled DS70175C-page 106 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 C2IP<2:0> bit Bit is unknown ...
Page 109
... DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 110
... Unimplemented: Read as ‘0’ DS70175C-page 108 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2EIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 111
... Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 112
... Note that only user interrupts with a priority level less can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to dis- able interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2006 Microchip Technology Inc. ...
Page 113
... ECAN2 Reception ECAN2 Transmission The DMA controller features eight identical data transfer channels. © 2006 Microchip Technology Inc. Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM ...
Page 114
... DMAC Sta- tus register (DMACS) to allow the DMAC error trap handler to determine the source of the Fault condition. Preliminary DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2006 Microchip Technology Inc. ...
Page 115
... Register Indirect Addressing with Post-Increment, which means the DMA RAM address will be incremented after every access. © 2006 Microchip Technology Inc. Any DMA channel can be configured to operate in Peripheral Indirect Addressing mode by setting the AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM source or destination address is partially derived from the peripheral as well as the DMA Address registers ...
Page 116
... Each channel has DMA RAM Write Collision (XWCOLx) and Peripheral Write Collision (PWCOLx) status bits in the DMAC Status register (DMACS) to allow the DMAC error trap handler to determine the source of the Fault condition. Preliminary © 2006 Microchip Technology Inc. ...
Page 117
... DMA0PAD should be loaded with the address of the A/D conversion result register DMA0PAD = (volatile unsigned int) &ADC1BUF0; // DMA transfer of 256 words of data DMA0CNT = 0x0100 ; //Clear the DMA0 Interrupt Flag IFS0bits.DMA0IF = 0; //Enable DMA0 Interrupts IEC0bits.DMA0IE = 1; //Enable the DMA0 Channel DMA0CONbits.CHEN = 1; © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 115 ...
Page 118
... Continuous, Ping-Pong modes disabled DS70175C-page 116 R/W-0 R/W-0 U-0 HALF NULLW — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MODE<1:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 119
... DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources. © 2006 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 120
... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 121
... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> R/W-0 R/W-0 R/W-0 PAD< ...
Page 122
... DS70175C-page 120 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 123
... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2006 Microchip Technology Inc. Preliminary PIC24H DS70175C-page 121 ...
Page 124
... DMA0STA register selected DS70175C-page 122 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 125
... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2006 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...
Page 126
... PIC24H NOTES: DS70175C-page 124 Preliminary © 2006 Microchip Technology Inc. ...
Page 127
... SOSCO SOSCEN Enable Oscillator SOSCI © 2006 Microchip Technology Inc. • The internal FRC oscillator can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • Clock switching between various clock sources • Programmable clock postscaler for system power savings • ...
Page 128
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 8-2: F OSC OSC IN Preliminary © 2006 Microchip Technology Inc. is divided OSC ). OSC ’, IN CALCULATION N1*N2 ...
Page 129
... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Reserved Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2006 Microchip Technology Inc. EQUATION 8-3: F OSC 0.8-8.0 MHz ...
Page 130
... Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70175C-page 128 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 131
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 ...
Page 132
... DS70175C-page 130 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 133
... Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.345 MHz) • • • 100001 = Center frequency – 11.625% (6.52 MHz) 100000 = Center frequency – 12% (6.49 MHz) © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 134
... FRC oscillator. Then the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. Preliminary and the CF © 2006 Microchip Technology Inc. ...
Page 135
... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2006 Microchip Technology Inc. and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 9-1 ...
Page 136
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary © 2006 Microchip Technology Inc. are eight possible ® DSC variant. If the ...
Page 137
... CK Data Latch Read LAT Read Port © 2006 Microchip Technology Inc. When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port ...
Page 138
... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. bit in either Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary in response to a © 2006 Microchip Technology Inc. ...
Page 139
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2006 Microchip Technology Inc. Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS<1:0> bits in the T1CON register. ...
Page 140
... DS70175C-page 138 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 141
... Timer8 clock and gate inputs are utilized for the 32-bit timer modules, but an inter- rupt is generated with the Timer3, Timer5, Ttimer7 and Timer9 interrupt flags. © 2006 Microchip Technology Inc. To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9 for 32-bit operation: 1. Set the corresponding T32 control bit. ...
Page 142
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70175C-page 140 (1) 1x Gate Sync PR2 PR3 Comparator LSB TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2006 Microchip Technology Inc. ...
Page 143
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2006 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary PIC24H TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70175C-page 141 ...
Page 144
... DS70175C-page 142 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 145
... External clock from pin TyCK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. © 2006 Microchip Technology Inc. U-0 U-0 (1) — — R/W-0 U-0 (1) — ...
Page 146
... PIC24H NOTES: DS70175C-page 144 Preliminary © 2006 Microchip Technology Inc. ...
Page 147
... ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2006 Microchip Technology Inc. Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or external clock ...
Page 148
... Timer selections may vary. Refer to the device data sheet for details. DS70175C-page 146 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 149
... TMRy register, are not required but may be advantageous for defining a pulse from a known event time boundary. © 2006 Microchip Technology Inc. The output compare module does not have to be dis- abled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register ...
Page 150
... Table 14-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM log (2) 10 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 10 Preliminary CALCULATING THE PWM PERIOD • (Timer Prescale Value bits = 16 MHz and a Timer2 CY © 2006 Microchip Technology Inc. ...
Page 151
... Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. Note: Only OC1 and OC2 can trigger a DMA data transfer. © 2006 Microchip Technology Inc 122 Hz 977 Hz ...
Page 152
... DS70175C-page 150 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 (1) OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 153
... SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) are moved to the receive buffer. If any transmit data has © 2006 Microchip Technology Inc. been written to the buffer register, the contents of the transmit buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer ...
Page 154
... SPI1IF or SPI2IF bit gets set as a result of an SPI1 or SPI2 byte or word transfer. 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2006 Microchip Technology Inc. ...
Page 155
... FIGURE 15-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24H (SPI Slave, Frame Slave) FIGURE 15-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24H (SPI Master, Frame Slave) © 2006 Microchip Technology Inc. PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb ...
Page 156
... Preliminary 4:1 6:1 8:1 6666.67 5000 2500 1666.67 1250 625 416.67 312.50 104.17 78.125 1250 833 625 313 208 156 © 2006 Microchip Technology Inc. ...
Page 157
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2006 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 158
... SPI modes (FRMEN = 1). DS70175C-page 156 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 159
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: Read as ‘0’ This bit must not be set to ‘1’ by the user application. © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — ...
Page 160
... PIC24H NOTES: DS70175C-page 158 Preliminary © 2006 Microchip Technology Inc. ...
Page 161
... I C master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, please refer to the “dsPIC30F Family Reference Manual” (DS70046). © 2006 Microchip Technology Inc Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable ...
Page 162
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2006 Microchip Technology Inc. ...
Page 163
... The control bit, IPMIEN, enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2006 Microchip Technology Inc. 16.8 General Call Address Support The general call address can address all devices. ...
Page 164
... SDAx is a ‘1’ and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The 2 master will set the I C master events interrupt flag and reset the master portion of the I Preliminary © 2006 Microchip Technology Inc port to its Idle state. ...
Page 165
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2006 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 166
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70175C-page 164 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master) Preliminary 2 C master) © 2006 Microchip Technology Inc. ...
Page 167
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2006 Microchip Technology Inc. U-0 U-0 R/C-0 HS — — ...
Page 168
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70175C-page 166 2 C slave device address byte. Preliminary © 2006 Microchip Technology Inc. ...
Page 169
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2006 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 170
... PIC24H NOTES: DS70175C-page 168 Preliminary © 2006 Microchip Technology Inc. ...
Page 171
... UART1 or UART2 transmission or reception DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2006 Microchip Technology Inc. • Fully Integrated Baud Rate Generator with 16-bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 172
... Desired Baud Rate Preliminary UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate denotes the instruction cycle clock /2). OSC CY © 2006 Microchip Technology Inc. /4 ...
Page 173
... Write 0x55 to UxTXREG – loads Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2006 Microchip Technology Inc. 17.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 17.2 “ ...
Page 174
... DS70175C-page 172 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary (2) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 175
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). 2: Bit availability depends on pin availability. © 2006 Microchip Technology Inc. MODE REGISTER (CONTINUED) x Preliminary PIC24H DS70175C-page 173 ...
Page 176
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 177
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2006 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary PIC24H ...
Page 178
... PIC24H NOTES: DS70175C-page 176 Preliminary © 2006 Microchip Technology Inc. ...
Page 179
... CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2006 Microchip Technology Inc. The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 180
... RXF10 Filter RXF9 Filter RXF8 Filter RXF7 Filter RXF6 Filter RXF5 Filter RXF4 Filter RXF3 Filter RXF2 Filter RXF1 Filter RXF0 Filter Buffer Preliminary RXM2 Mask RXM1 Mask RXM0 Mask Control CPU Configuration Bus Logic Interrupts © 2006 Microchip Technology Inc. ...
Page 181
... The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2006 Microchip Technology Inc. Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation ...
Page 182
... Receiver Error Passive: The RXEP bit indicates that the receive error counter has exceeded the error passive limit of 127 and the module has gone into error passive state. Preliminary © 2006 Microchip Technology Inc. ...
Page 183
... TXERRn bit will be set and the error condition may cause an interrupt. If the message loses arbitration during the transmission attempt, the TXLARBn bit is set. No interrupt is generated to signal the loss of arbitration. © 2006 Microchip Technology Inc. 18.5.4 AUTOMATIC PROCESSING OF REMOTE TRANSMISSION REQUESTS ...
Page 184
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 sec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Preliminary . Also, by definition, Q Sync © 2006 Microchip Technology Inc. ...
Page 185
... CAN module allows the user to choose between sam- pling three times at the same point or once at the same point, by setting or clearing the SAM bit (CiCFG2<6>). © 2006 Microchip Technology Inc. Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters ...
Page 186
... Use buffer window 0 DS70175C-page 184 R/W-0 R/W-0 R/W-1 ABAT CANCKS U-0 R/W-0 — CANCAP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared CY OSC Preliminary R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 U-0 R/W-0 — — WIN bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 187
... DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> .... 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — ...
Page 188
... TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70175C-page 186 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 189
... Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer .... 00001 = TRB1 buffer 00000 = TRB0 buffer © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 FSA< ...
Page 190
... RB30 buffer .... 000001 = TRB1 buffer 000000 = TRB0 buffer DS70175C-page 188 R-0 R-0 R-0 FBP<5:0> R-0 R-0 R-0 FNRB<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 191
... Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit bit 1 RBIF: RX Buffer Interrupt Flag bit bit 0 TBIF: TX Buffer Interrupt Flag bit © 2006 Microchip Technology Inc. R-0 R-0 R-0 TXBP RXBP TXWAR U-0 R/C-0 R/C-0 — ...
Page 192
... DS70175C-page 190 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 — FIFOIE RBOVIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 RBIE TBIE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 193
... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits © 2006 Microchip Technology Inc. R-0 R-0 R-0 TERRCNT<7:0> R-0 R-0 R-0 RERRCNT<7:0> Unimplemented bit, read as ‘0’ ...
Page 194
... DS70175C-page 192 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 BRP<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared CAN CAN CAN CAN Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 195
... Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Buffer Segment 1 bits 111 = Length 000 = Length bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length 000 = Length © 2006 Microchip Technology Inc. U-0 U-0 — — R/W-x R/W-x SEG1PH<2:0> Unimplemented bit, read as ‘0’ ...
Page 196
... R/W-0 F2BP<3:0> R/W-0 R/W-0 R/W-0 F0BP<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 FLTEN9 FLTEN8 bit 8 R/W-1 R/W-1 FLTEN1 FLTEN0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 197
... F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits bit 11-8 F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits bit 7-4 F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits bit 3-0 F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 F6BP<3:0> R/W-0 R/W-0 R/W-0 F4BP< ...
Page 198
... F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits DS70175C-page 196 R/W-0 R/W-0 R/W-0 F14BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 199
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘ Message address bit EIDx must be ‘ © 2006 Microchip Technology Inc. R/W-x R/W-x R/W-x SID7 SID6 SID5 U-0 R/W-x U-0 — ...
Page 200
... Acceptance Mask 0 registers contain mask DS70175C-page 198 R/W-0 R/W-0 F6MSK<1:0> F5MSK<1:0> R/W-0 R/W-0 F2MSK<1:0> F1MSK<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 F4MSK<1:0> bit 8 R/W-0 R/W-0 R/W-0 F0MSK<1:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...