DSPIC30F6011-30I/PF Microchip Technology, DSPIC30F6011-30I/PF Datasheet
DSPIC30F6011-30I/PF
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DSPIC30F6011-30I/PF Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70117F ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... High-Performance Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... Detects clock failure and switches to on-chip low power RC oscillator • Programmable code protection • In-Circuit Serial Programming™ (ICSP™) • Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes dsPIC30F6011/6012/6013/6014 Controller Families Program Memory Device Pins Bytes Instructions dsPIC30F6011 ...
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... SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC/EMUC/AN1/V -/CN3/RB1 15 REF PGD/EMUD/AN0/V +/CN2/RB0 16 REF *dsPIC30F6011A recommended for new designs Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 dsPIC30F6011 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 ...
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... Pin Diagrams (Continued) 64-Pin TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC/EMUC/AN1/V -/CN3/RB1 15 REF PGD/EMUD/AN0/V +/CN2/RB0 16 REF *dsPIC30F6012A recommended for new designs Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70117F-page 4 ...
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... INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 *dsPIC30F6013A recommended for new designs Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 dsPIC30F6013 EMUC1/SOSCO/T1CK/CN0/RC14 60 EMUD1/SOSCI/CN1/RC13 59 58 EMUC2/OC1/RD0 57 IC4/RD11 IC3/RD10 56 IC2/RD9 55 IC1/RD8 54 INT4/RA15 53 52 INT3/RA14 ...
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... Pin Diagrams (Continued) 80-Pin TQFP 1 COFS/RG15 T2CK/RC1 2 3 T3CK/RC2 4 T4CK/RC3 5 T5CK/RC4 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 *dsPIC30F6014A recommended for new designs Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 DS70117F-page 7 ...
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... NOTES: DS70117F-page 8 © 2006 Microchip Technology Inc. ...
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... Programmer’s Reference Manual” (DS70157). © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 This document contains specific information for the dsPIC30F6011/6012/6013/6014 Digital Signal Control- ler (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture ...
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... FIGURE 1-1: dsPIC30F6011/6012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (Up to 144 Kbytes) Data EEPROM ( Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect CAN1, 12-bit ADC CAN2 Timers *Present in the dsPIC30F6014 only. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM 16 Address Address Latch Latch RAGU Y AGU ...
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... Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Buffer Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes ...
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... NOTES: DS70117F-page 14 © 2006 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... DSP ACCA Accumulators ACCB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The fol- lowing instructions and data sizes are supported: 1. DIVF - 16/16 signed fractional divide 2 ...
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... EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70117F-page 20 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2006 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When satu- ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70117F-page 24 © 2006 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG< ...
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... FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6011/6013 Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions) Reserved (Read ‘0’s) Data EEPROM (2 Kbytes) Reserved UNITID (32 instr.) Reserved Device Configuration ...
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... Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24-bit wide program memory. Consequently, instructions are always However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2 “ ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn<0> ...
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... FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space 15 EA<15> Data Space 15 EA EA<15> Upper Half of Data Space is Mapped into Program Space BSET CORCON,#2 ; PSV bit set MOV #0x01 Set PSVPAG register MOV W0, PSVPAG MOV 0x8000 Access program memory location ...
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... MAC class instructions. The data space memory maps are shown in Figure 3-8 and Figure 3-9. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 3.2.2 DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses ...
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... FIGURE 3-7: DATA SPACE MEMORY MAP FOR dsPIC30F6011/6013 MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 6 Kbyte SRAM Space 0x17FF 0x1801 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70117F-page 32 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...
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... Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 16 bits MSB LSB SFR Space X Data RAM (X) Y Data RAM (Y) X Data Unimplemented (X) LSB Address 0x0000 0x07FE 0x0800 8 Kbyte ...
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... FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read) Indirect EA from any W TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES Attempted Operation Data Returned unimplemented address used to access Y data space in a MAC instruction ...
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... Additionally, the whole of X data space is addressable using MOV instructions, which support memory direct addressing with a 16-bit address field. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 3.2.6 SOFTWARE STACK The dsPIC DSC devices contain a software stack. W15 is used as the Stack Pointer. ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) SR 0042 CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT ...
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... NOTES: DS70117F-page 38 © 2006 Microchip Technology Inc. ...
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... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 4.1.1 FILE REGISTER INSTRUCTIONS Most File register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the effective address calculation associated with any W register important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... NOTES: DS70117F-page 44 © 2006 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the con- trol and status flags for the processor exceptions ...
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... Interrupt Priority The user assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx regis- ter(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
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... Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Note that many of these trap conditions can only be detected when they occur. Consequently, the question- able instruction is allowed to complete prior to trap exception processing ...
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... Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address. 6. Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN instruction ...
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... AIVT may be used for other purposes. AIVT is not a protected section and may be freely programmed by the user. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 5.6 Fast Context Saving A context saving option is available using shadow reg- isters. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers W0 through W3 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70117F-page 56 © 2006 Microchip Technology Inc. ...
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... Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software. They are cleared in hardware at the com- pletion of the write operation ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70117F-page 62 © 2006 Microchip Technology Inc. ...
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... WR Port Read LAT Read Port © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
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... RA14 RA13 RA12 LATA 02C4 LATA15 LATA14 LATA13 LATA12 Note 1: PORTA is not implemented in the dsPIC30F6011/6012 devices. 2: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-2: PORTB REGISTER MAP FOR dsPIC30F6011/6012/6013/6014 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 ...
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... LATF 02E2 — — — — Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-9: PORTG REGISTER MAP FOR dsPIC30F6011/6012/6013/6014 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 ...
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... Sleep mode, when the clocks are disabled. There are exter- nal signals (CN0 through CN23) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 8-10: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F6011/6012 (BITS 15-8) SFR Addr. Bit 15 Bit 14 Name ...
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... NOTES: DS70117F-page 68 © 2006 Microchip Technology Inc. ...
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... SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value preloaded into the Period register PR1, then resets to ‘ ...
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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register and is then Reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for ...
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... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode. See Section 9.0 “ ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70117F-page 74 ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 TGATE ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70117F-page 78 © 2006 Microchip Technology Inc. ...
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... Note: Timer Configuration bit T45 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and ...
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... Equal Reset 0 T5IF Event Flag 1 TGATE T5CK Note: In the dsPIC30F6011 and dsPIC30F6012 devices, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: 1: TCS = 1 (16-bit counter) 2: TCS = 0, TGATE = 1 (Gated Time Accumulation) DS70117F-page 80 PR4 Comparator x 16 TMR4 Q ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70117F-page 82 © 2006 Microchip Technology Inc. ...
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... Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain capture channels (i ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70117F-page 86 © 2006 Microchip Technology Inc. ...
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... Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...
Page 91
... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 92
TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
Page 93
... Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit ...
Page 94
... FIGURE 14-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDIx bit 0 SDOx SS and FSYNC Control SSx SCKx Note FIGURE 14-2: SPI MASTER/SLAVE CONNECTION SPI Master Serial Input Buffer (SPIxBUF) Shift Register (SPIxSR) MSb PROCESSOR 1 Note DS70117F-page 92 Internal Data Bus Write SPIxBUF ...
Page 95
... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
Page 96
TABLE 14-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Note: Refer to “dsPIC30F Family Reference ...
Page 97
... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 15.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
Page 98
... FIGURE 15-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70117F-page 96 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
Page 99
... SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 100
... MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 15.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching ...
Page 101
... Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2 15. Master Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition ...
Page 102
... BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbi- tration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high ...
Page 103
TABLE 15- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...
Page 104
... NOTES: DS70117F-page 102 © 2006 Microchip Technology Inc. ...
Page 105
... UTXBRK Data UxTX Parity Note © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 106
... FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70117F-page 104 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 107
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 16.3 Transmitting Data 16.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 108
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 109
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode in which a 9th bit (URX8) value of ‘ ...
Page 110
... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input cap- ture module to detect the falling and rising edges of the Start bit ...
Page 111
TABLE 16-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 112
... NOTES: DS70117F-page 110 © 2006 Microchip Technology Inc. ...
Page 113
... CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 114
... FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). DS70117F-page 112 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 ...
Page 115
... Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 116
... Message Reception 17.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can ...
Page 117
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 118
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt. • ...
Page 119
... The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec fixed tive bit ...
Page 120
TABLE 17-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> C1RXF1SID 0308 — — ...
Page 121
TABLE 17-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1EID 0352 Transmit Buffer 1 Extended Identifier <17:14> C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier <5:0> C1TX1B1 0356 Transmit Buffer 1 Byte 1 ...
Page 122
TABLE 17-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1INTE 0398 — — — — C1EC 039A Transmit Error Count Register Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference ...
Page 123
TABLE 17-2: CAN2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2RXF0SID — — — 03C0 C2RXF0EIDH 03C2 — — — — C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier <5:0> C2RXF1SID — — — ...
Page 124
TABLE 17-2: CAN2 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2TX1EID 0412 Transmit Buffer 1 Extended Identifier <17:14> C2TX1DLC 0414 Transmit Buffer 1 Extended Identifier <5:0> C2TX1B1 0416 Transmit Buffer 1 Byte 1 ...
Page 125
TABLE 17-2: CAN2 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2INTF 0456 RX0OVR RX1OVR TXBO TXEP C2INTE 0458 — — — — C2EC 045A Transmit Error Count Register Legend uninitialized bit ...
Page 126
... NOTES: DS70117F-page 124 © 2006 Microchip Technology Inc. ...
Page 127
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. ...
Page 128
... FIGURE 18-1: DCI MODULE BLOCK DIAGRAM F OSC Word Size Selection bits Frame Length Selection bits DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70117F-page 126 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer ...
Page 129
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the Frame Synchronization (COFSM< ...
Page 130
... SLAVE FRAME SYNC OPERATION When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sam- pled high (see Figure 18-2) ...
Page 131
... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 132
... SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sam- pled on the falling edge of the CSCK signal ...
Page 133
... DCI module. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 134
... SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indi- cate the current active time slot. These bits will corre- spond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers ...
Page 135
... The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2 18.7.1 I LENGTH SELECTION The WS and COFSG control bits are set to produce the ...
Page 136
TABLE 18-2: DCI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DCICON1 0240 DCIEN — DCISIDL — DCICON2 0242 — — — — DCICON3 0244 — — — — DCISTAT 0246 — — — — ...
Page 137
... AN14 1111 AN15 V AN1 © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The ADC module has six 16-bit registers: • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) • ADC Control Register 3 (ADCON3) • ADC Input Select Register (ADCHS) • ADC Port Configuration Register (ADPCFG) • ...
Page 138
... ADC Result Buffer The module contains a 16-word dual port read only buffer, called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 139
... EQUATION 19-1: ADC CONVERSION CLOCK (0.5 * (ADCS<5:0> © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V Specifications section for minimum T operating conditions ...
Page 140
... ADC Speeds The dsPIC30F 12-bit ADC specifications permit a max- imum of 200 ksps sampling rate. The table below sum- marizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES ...
Page 141
... Set SSRC<2.0> = 111 in the ADCON1 register to enable the auto convert option. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register. • Write the SMPI<3.0> control bits in the ADCON2 register for the desired number of conversions between interrupts. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 dsPIC30F6014 ...
Page 142
... FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START SAMPLING TIME T SAMP = ADCLK SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM DS70117F-page 140 T SAMP = CONV CONV = © 2006 Microchip Technology Inc. AD ...
Page 143
... Note: C value depends on device package and is not tested. Effect of C PIN © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 required to charge the capacitor C impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. To minimize the effects ...
Page 144
... Module Power-down Modes The module has 2 internal Power modes. When the ADON bit is ‘1’, the module is in Active mode fully powered and functional. When ADON is ‘0’, the module is in Off mode. The dig- ital and analog portions of the circuit are disabled for maximum current savings ...
Page 145
... ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 19.14 Connection Considerations The analog inputs have diodes to V protection. This requires that the analog input be between V DD range by greater than 0 ...
Page 146
TABLE 19-2: A/D CONVERTER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 147
... In the Idle mode, the clock sources are still active but the CPU is shut off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 148
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2. XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 149
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...
Page 150
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> Configuration bits that select one of four oscillator groups, b) and FPR<3:0> Configuration bits that select one of 13 oscillator choices within the primary group. ...
Page 151
... Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 20.2.6 LOW POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT, and clock monitor circuits ...
Page 152
... If the oscillator has a very slow start-up time coming out of POR, BOR or Sleep possible that the PWRT timer will expire before the oscillator has started. In such cases, the FSCM will be activated and the FSCM will initiate a clock failure trap, and the COSC<1:0> bits are loaded with FRC oscillator selection ...
Page 153
... Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 154
... FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 155
... Specifications in the specific device data sheet for BOR voltage limit specifications. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 156
... Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: ...
Page 157
... Trap Reset 0x000000 Illegal Operation Reset 0x000000 Legend unchanged Note: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 158
... Watchdog Timer (WDT) 20.4.1 WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT reset the processor in the event of a software mal- function. The WDT is a free-running timer which runs off an on-chip RC oscillator, requiring no external com- ponent. Therefore, the WDT timer will continue to oper- ate even if the main processor clock (e ...
Page 159
... CPU and instruction execution begins immedi- ately, starting with the instruction following the PWRSAV instruction. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Any interrupt that is individually enabled (using IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR ...
Page 160
... Note: In the dsPIC30F6011 and dsPIC30F6013 devices, the DCIMD bit is readable and writable, and will be read as ‘1’ when set. DS70117F-page 158 20.9 In-Circuit Debugger ® ...
Page 161
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 PMD1 0770 T5MD T4MD T3MD T2MD T1MD PMD2 0772 ...
Page 162
... NOTES: DS70117F-page 160 © 2006 Microchip Technology Inc. ...
Page 163
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 164
... All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
Page 165
... Y data space prefetch address register for DSP instructions {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0..W15} { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } {W4 ...
Page 166
... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 167
... DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 168
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 169
... RRC RRC f RRC f,WREG RRC Ws,Wd © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 170
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd ...
Page 171
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 172
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 173
... Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
Page 174
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 175
... Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 176
... TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F601x-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F601x-20I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F601x-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: ∑ ...
Page 177
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C ...
Page 178
... TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current (I ) IDLE DC51a 6.3 9 DC51b 5.9 9 DC51c 5.7 9 DC51e 16 21 DC51f 15 21 DC51g 15 21 DC50a 10 15 DC50b 10 15 DC50c 10 15 DC50e 21 30 DC50f 20 30 DC50g 19 30 DC43a 15 23 ...
Page 179
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T Units A 25° ...
Page 180
... TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No Input Low Voltage DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 181
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max (2) — — ...
Page 182
... TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD high to low LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: ...
Page 183
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T (1) Min ...
Page 184
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
Page 185
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 186
... TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 187
... TABLE 23-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65 Note 1: Change of LPRC frequency as V © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 = 1 / MIPS PLLx)/4 [since there are 4 Q clocks per instruction OSC -40°C T -40°C T Min Typ Max ...
Page 188
... FIGURE 23-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 23-3 for load conditions. TABLE 23-20: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 23-2 and Table 23-11 for BOR. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 SY10 SY13 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 190
... TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY25 T Brown-out Reset Pulse Width BOR SY30 T Oscillation Start-up Timer Period OST SY35 T Fail-Safe Clock Monitor Delay FSCM Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 191
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: Timer1 is a Type A. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature Min Typ Synchronous, 0 ...
Page 192
... TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T - Delay from External TxCK Clock CKEXT Edge to Timer Increment ...
Page 193
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V ...
Page 194
... FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 195
... CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 70 LSb ...
Page 196
... TABLE 23-29: DCI MODULE (MULTICHANNEL CHARACTERISTICS Param Symbol Characteristic No. CS10 Tc CSCK Input Low Time SCKL (CSCK pin is an input) CSCK Output Low Time (CSCK pin is an output) CS11 Tc CSCK Input High Time SCKH (CSCK pin is an input) CSCK Output High Time ...
Page 197
... These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 CS62 CS71 CS72 CS76 CS76 Standard Operating Conditions: 2.5V to 5.5V ...
Page 198
... TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. CS78 T Fall Time, SYNC, SDATA_OUT FACL CS80 T Output valid delay from rising OVDACL edge of BIT_CLK Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. ...
Page 199
... SP11 SCK X (CKP = 1) SDO MSb X SP40 SP30,SP31 SDI X MSb IN SP41 Note: Refer to Figure 23-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ (4) — — (4) — — (4) — ...
Page 200
... TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SP10 TscL SCK output low time X SP11 TscH SCK output high time X SP20 TscF SCK output fall time X SP21 TscR SCK output rise time X SP30 TdoF SDO ...