IC ENCORE MCU FLASH 2K 28SOIC

 

Z8F0213SJ005EC

Manufacturer Part NumberZ8F0213SJ005EC
DescriptionIC ENCORE MCU FLASH 2K 28SOIC
ManufacturerZilog
SeriesEncore!® XP®
Z8F0213SJ005EC datasheets

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Warranty: 60 days

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Specifications of Z8F0213SJ005EC

Core ProcessorZ8Core Size8-Bit
Speed5MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDTNumber Of I /o24
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size512 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 105°C
Package / Case28-SOIC (7.5mm Width)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names269-3464  
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Page 176/247

Download datasheet (4Mb)Embed
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Unintentional accesses to the oscillator control register can actually stop the chip by
Caution:
switching to a non-functioning oscillator. To prevent this condition, the oscillator con-
trol block employs a register unlocking/locking scheme.
OSC Control Register Unlocking/Locking
To write the oscillator control register, unlock it by making two writes to the OSCCTL
register with the values
changes the value of the actual register and returns the register to a locked state. Any other
sequence of oscillator control register writes has no effect. The values written to unlock
the register must be ordered correctly, but are not necessarily consecutive. It is possible to
write to or read from other registers within the unlocking/locking operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the oscillator control register.
The internal precision oscillator is enabled by default. If the user code changes to a
different oscillator, it is appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
®
Z8 Encore! XP
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate, allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available if the Watchdog Timer is the primary oscillator. It is also unavailable
if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the
Watchdog Timer reset function outlined in the
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be deasserted in
the OSCCTL register).
PS024314-0308
followed by
. A third write to the OSCCTL register
E7H
18H
F0823 Series devices can generate non-maskable interrupt-like events
Watchdog Timer
®
Z8 Encore! XP
F0823 Series
Product Specification
on page 87.
Oscillator Control
166

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