IC ENCORE MCU FLASH 2K 28SOIC

 

Z8F0213SJ005EC

Manufacturer Part NumberZ8F0213SJ005EC
DescriptionIC ENCORE MCU FLASH 2K 28SOIC
ManufacturerZilog
SeriesEncore!® XP®
Z8F0213SJ005EC datasheets

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Warranty: 60 days

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Specifications of Z8F0213SJ005EC

Core ProcessorZ8Core Size8-Bit
Speed5MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDTNumber Of I /o24
Program Memory Size2KB (2K x 8)Program Memory TypeFLASH
Ram Size512 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 105°C
Package / Case28-SOIC (7.5mm Width)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names269-3464  
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Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 1 Register (IRQ1)
BITS
7
6
PA7VI
PA6CI
FIELD
0
0
RESET
R/W
R/W
R/W
ADDR
PA7VI—Port A7 Interrupt Request
0 = No interrupt request is pending for GPIO Port A
1 = An interrupt request from GPIO Port A
PA6CI—Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Comparator
1 = An interrupt request from GPIO Port A or Comparator
PAxI—Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x
1 = An interrupt request from GPIO Port A pin x is awaiting service
where x indicates the specific GPIO Port pin number (0–5)
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 register to determine if any interrupt requests are pending.
PS024314-0308
(Table
35) stores interrupt requests for both
5
4
3
PA5I
PA4I
PA3I
0
0
0
R/W
R/W
R/W
FC3H
(Table
36) stores interrupt requests for both
®
Z8 Encore! XP
F0823 Series
Product Specification
2
1
0
PA2I
PA1I
PA0I
0
0
0
R/W
R/W
R/W
Interrupt Controller
59