IC ENCORE XP MCU FLASH 1K 20DIP

 

Z8F011APH020EC

Manufacturer Part NumberZ8F011APH020EC
DescriptionIC ENCORE XP MCU FLASH 1K 20DIP
ManufacturerZilog
SeriesEncore!® XP®
Z8F011APH020EC datasheets

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Warranty: 60 days

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Specifications of Z8F011APH020EC

Core ProcessorZ8Core Size8-Bit
Speed20MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, LVD, POR, PWM, WDTNumber Of I /o17
Program Memory Size1KB (1K x 8)Program Memory TypeFLASH
Eeprom Size16 x 8Ram Size256 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantData Converters-
Other names269-3312  
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Page 190/282

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PrevNext
Breakpoints in Flash Memory
The
instruction is opcode
BRK
byte in Flash memory. To implement a Breakpoint, write
address, overwriting the current instruction. To remove a Breakpoint, the corresponding
page of Flash memory must be erased and reprogrammed with the original data.
Runtime Counter
The On-Chip Debugger contains a 16-bit Runtime Counter. It counts system clock cycles
between Breakpoints. The counter starts counting when the On-Chip Debugger leaves
DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches
the maximum count of
On-Chip Debugger Commands
The host communicates to the on-chip debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In DEBUG mode, all OCD commands become available unless the user code and
control registers are protected by programming the Flash Read Protect Option bit (
The Flash Read Protect Option bit prevents the code in memory from being read out of the
Z8 Encore! XP F082A Series products. When this option is enabled, several of the OCD
commands are disabled.
commands. Each OCD command is described in further detail in the bulleted list follow-
ing this table.
Table 106
device is not in DEBUG mode (normal operation) and those commands that are disabled
by programming the Flash Read Protect Option bit.
Command
Debug Command
Read OCD Revision
Reserved
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
PS022825-0908
, which corresponds to the fully programmed state of a
00H
.
FFFFH
Table 106
on page 184 is a summary of the On-chip debugger
on page 184 also indicates those commands that operate when the
Enabled when
NOT in DEBUG
Byte
mode?
00H
Yes
01H
02H
Yes
03H
04H
Yes
05H
Yes
06H
07H
®
Z8 Encore! XP
F082A Series
Product Specification
to the required break
00H
FRP
Disabled by
Flash Read Protect Option Bit
Cannot clear DBGMODE bit
Disabled
Disabled
On-Chip Debugger
179
).