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Z8F011APH020EC
Z8F011APH020EC | |
|---|---|
| Manufacturer Part Number | Z8F011APH020EC |
| Description | IC ENCORE XP MCU FLASH 1K 20DIP |
| Manufacturer | Zilog |
| Series | Encore!® XP® |
| Z8F011APH020EC datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of Z8F011APH020EC | |||
|---|---|---|---|
| Core Processor | Z8 | Core Size | 8-Bit |
| Speed | 20MHz | Connectivity | IrDA, UART/USART |
| Peripherals | Brown-out Detect/Reset, LED, LVD, POR, PWM, WDT | Number Of I /o | 17 |
| Program Memory Size | 1KB (1K x 8) | Program Memory Type | FLASH |
| Eeprom Size | 16 x 8 | Ram Size | 256 x 8 |
| Voltage - Supply (vcc/vdd) | 2.7 V ~ 3.6 V | Oscillator Type | Internal |
| Operating Temperature | -40°C ~ 105°C | Package / Case | 20-DIP (0.300", 7.62mm) |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Data Converters | - |
| Other names | 269-3312 | ||
PrevNext
function). (Push-pull output)
1 = The source current for the associated pin is disabled (open-drain mode).
Port A–D High Drive Enable Sub-Registers
The Port A–D High Drive Enable sub-register
A–D Control register by writing
the Port A–D High Drive Enable sub-registers to 1 configures the specified port pins for
high current output drive operation. The Port A–D High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
Table 22. Port A–D High Drive Enable Sub-Registers (PxHDE)
7
6
BITS
PHDE7
PHDE6
FIELD
0
0
RESET
R/W
R/W
R/W
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
ADDR
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–D Stop Mode Recovery Source Enable Sub-Registers
The Port A–D Stop Mode Recovery Source Enable sub-register
through the Port A–D Control register by writing
Setting the bits in the Port A–D Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
Table 23. Port A–D Stop Mode Recovery Source Enable Sub-Registers (PxSMRE)
7
6
BITS
PSMRE7
PSMRE6
FIELD
0
0
RESET
R/W
R/W
R/W
If 05H in Port A–D Address Register, accessible through the Port A–D Control Register
ADDR
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled
0 = The Port pin is not configured as a Stop Mode Recovery source. Transitions on this pin
PS022825-0908
(Table
to the Port A–D Address register. Setting the bits in
04H
5
4
3
PHDE5
PHDE4
PHDE3
0
0
0
R/W
R/W
R/W
05H
5
4
3
PSMRE5
PSMRE4
PSMRE3
0
0
0
R/W
R/W
R/W
®
Z8 Encore! XP
F082A Series
Product Specification
22) is accessed through the Port
2
1
0
PHDE2
PHDE1
PHDE0
0
0
0
R/W
R/W
R/W
(Table
23) is accessed
to the Port A–D Address register.
2
1
0
PSMRE2
PSMRE1
PSMRE0
0
0
0
R/W
R/W
R/W
General-Purpose Input/Output
49
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