IC ENCORE XP MCU FLASH 1K 20DIP

 

Z8F011APH020EC

Manufacturer Part NumberZ8F011APH020EC
DescriptionIC ENCORE XP MCU FLASH 1K 20DIP
ManufacturerZilog
SeriesEncore!® XP®
Z8F011APH020EC datasheets

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Warranty: 60 days

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Specifications of Z8F011APH020EC

Core ProcessorZ8Core Size8-Bit
Speed20MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, LVD, POR, PWM, WDTNumber Of I /o17
Program Memory Size1KB (1K x 8)Program Memory TypeFLASH
Eeprom Size16 x 8Ram Size256 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantData Converters-
Other names269-3312  
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Interrupt Controller
The interrupt controller on the Z8 Encore! XP F082A Series products prioritizes the inter-
rupt requests from the on-chip peripherals and the GPIO port pins. The features of inter-
rupt controller include:
20 possible interrupt sources with 18 unique interrupt vectors:
Twelve GPIO port pin interrupt sources (two interrupt vectors are shared).
Eight on-chip peripheral interrupt sources (two interrupt vectors are shared).
Flexible GPIO interrupts:
Eight selectable rising and falling edge GPIO interrupts.
Four dual-edge interrupts.
Three levels of individually programmable interrupt priority.
Watchdog Timer and LVD can be configured to generate an interrupt.
Supports vectored as well as polled interrupts
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is
completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. For more information on interrupt ser-
vicing by the eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) available for
download at www.zilog.com.
Interrupt Vector Listing
Table 32
on page 56 lists all of the interrupts available in order of priority. The interrupt
vector is stored with the most-significant byte (MSB) at the even Program Memory
address and the least-significant byte (LSB) at the following odd Program Memory
address.
Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt
Note:
is unavailable on devices not containing an ADC.
PS022825-0908
®
Z8 Encore! XP
F082A Series
Product Specification
Interrupt Controller
55