ST10F272Z2Q3 STMicroelectronics, ST10F272Z2Q3 Datasheet
ST10F272Z2Q3
Specifications of ST10F272Z2Q3
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ST10F272Z2Q3 Summary of contents
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... Two multi-functional general purpose timer units with 5 timers ■ Two 16-channel capture / compare units ■ 4-channel PWM unit + 4-channel XPWM Table 1. Device summary Order code Package ST10F272Z2Q3 PQFP144 ST10F272Z2T3 LQFP144 January 2008 PQFP144 ( 3.4mm) (Plastic Quad Flat Package) ■ A/D converter – 24-channel 10-bit – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST10F272Z2 5.5.6 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 13.2 I/O special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST10F272Z2 21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 25.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 25.7.1 ...
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ST10F272Z2 List of tables Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 50. Reset event ...
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ST10F272Z2 List of figures Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. ST10F272Z2 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST10F272Z2 1 Description The ST10F272Z2 device is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F272Z2 combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on- chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F272Z2 is processed in 0.18 µ ...
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Description CLKOUT function can output either the CPU clock (like in ST10F269 software programmable prescaled value of the CPU clock. On-chip RAM memory has been increased (Flash size remained the same). PLL multiplication factors have been adapted to ...
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ST10F272Z2 Figure 1. Logic symbol XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V AGND ST10F272Z2 NMI STBY READY ALE WRL Port 5 16-bit Description Port 0 16-bit ...
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Pin data 2 Pin data Figure 2. Pin configuration (top view) P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / ...
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ST10F272Z2 Table 2. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O 12 P8.0 ...
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Pin data Table 2. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - ...
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ST10F272Z2 Table 2. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. I/O ...
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Pin data Table 2. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 ...
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ST10F272Z2 Table 2. Pin description (continued) Symbol Pin Type STBY P0L.0 -P0L.7, 100-107, P0H.0 108, I/O P0H.1 - 111-117 P0H.7 118-125 I/O 128-135 P1L.0 - P1L.7 P1H.0 - P1H.7 132 I 133 I 134 I ...
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Pin data Table 2. Pin description (continued) Symbol Pin Type XTAL1 138 I XTAL2 137 O XTAL3 143 I XTAL4 144 O RSTIN 140 I RSTOUT 141 O NMI 142 AREF AGND RPD ...
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ST10F272Z2 3 Functional description The architecture of the ST10F272Z2 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure ...
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Memory organization 4 Memory organization The memory space of the ST10F272Z2 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory ...
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ST10F272Z2 After reset the XRAM2 is mapped from address 09’0000h. XRAM2 represents also the Stand-by RAM, which can be maintained biased through EA / VSTBY pin when main supply VDD is turned off. As the XRAM appears like external memory, ...
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Memory organization (only word accesses are possible). Two waitstates give an access time of 62 MHz CPU clock. No tristate waitstate is used. I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The ...
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ST10F272Z2 Figure 4. ST10F272Z2 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value) Code Page Segment Segment FF FFFF 1023 11 FFFF 255 17 Ext. Memory 11 0000 10 FFFF 16 Ext. Memory 10 0000 0F FFFF XRAM2 ...
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Internal Flash memory 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed by one matrix module, 256 KBytes wide. This module is on ST10 Internal bus called IFLASH Figure 5. Flash structure The programming operations ...
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ST10F272Z2 5.2.2 Modules structure The IFLASH module is composed by a bank (Bank 0) of 256 Kbyte of Program Memory divided in 8 sectors (B0F0...B0F7). Bank 0 contains also a reserved sector named Test- Flash. The Addresses from 0x08 0000 ...
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Internal Flash memory When Bootstrap mode is entered: ● Test-Flash is seen and available for code fetches (address 00’0000h) ● User I-Flash is only available for read and write accesses ● Write accesses must be made with addresses starting in ...
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ST10F272Z2 5.3 Write operation The Flash module have one single register interface mapped in the memory space of the IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low ...
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Internal Flash memory 5.4 Register description 5.4.1 Flash control register 0 low The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High (FCR0H) is used to enable and to monitor all the write operations on ...
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ST10F272Z2 5.4.2 Flash control register 0 high The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low (FCR0L) is used to enable and to monitor all the write operations on the IFLASH. The user has ...
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Internal Flash memory Table 9. Flash control register 0 high (continued) Bit Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the ...
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ST10F272Z2 5.4.4 Flash control register 1 high The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low (FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of ...
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Internal Flash memory 5.4.6 Flash data register 0 high FDR0H (0x08 000A DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 Table 14. Flash data register 0 ...
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ST10F272Z2 5.4.9 Flash address register low FARL (0x08 0010 ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Table 17. Flash address register low Bit Address 15:2 These bits must be written with the ...
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Internal Flash memory 5.4.11 Flash error register Flash Error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit ...
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ST10F272Z2 5.5 Protection strategy The protection bits are stored in Non-Volatile Flash cells inside IFLASH module, that are read once at reset and stored in 4 Volatile registers. Before they are read from the Non- Volatile cells, all the available ...
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... Test Interface. If programmed the contrary, all the DBGP debug features, the Test Interface and all the Flash Test Modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. 5.5.4 Flash non-volatile access protection register 1 low ...
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ST10F272Z2 5.5.5 Flash non-volatile access protection register 1 high FNVAPR1H (0x08 DFBE PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 Table 23. Flash non-volatile access protection register 1 high Bit Protections ...
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Internal Flash memory way can be executed a maximum of 16 times. To execute the above described operations, the Flash has to be temporary unprotected (See Trying to write into the access protected Flash from internal RAM or external memories ...
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ST10F272Z2 To restore the Access Protection necessary to reset the microcontroller or to write at 0 the bit TAUB in XFVTAUR0. Internal Flash memory 41/189 ...
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Internal Flash memory 5.6 Write operation examples In the following, examples for each kind of Flash write operation are presented. Note: The write operation commands must be executed from another memory (internal RAM or external memory ST10F269 device. ...
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ST10F272Z2 Suspend and resume Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way: FCR0H |= 0x4000; Then the operation can be resumed in the following way: FCR0H |= 0x0800; FCR0H |= 0x8000; Before ...
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Internal Flash memory A Sector Erase can be suspended by setting SUSP bit. ● To perform a Word Program operation during Erase Suspend, firstly bits SUSP and SER must be reset, then bit WPG and WMS can be set. ● ...
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ST10F272Z2 5.7 Write operation summary In general, each write operation is started through a sequence of 3 steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register ...
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Bootstrap loader 6 Bootstrap loader ST10F272Z2 implements Boot capabilities in order to: ● Support bootstrap via UART or bootstrap via CAN for the standard bootstrap. ● Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different way. ...
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ST10F272Z2 6.3 Alternate and selective boot mode (ABM and SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check The ...
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Central processing unit (CPU) 7 Central processing unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask ...
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ST10F272Z2 7.1 Multiplier-accumulator unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to ...
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Central processing unit (CPU) 7.2 Instruction set summary The Table 27 lists the instructions of the ST10F272Z2. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 27. Standard instruction set summary Mnemonic ADD(B) ...
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ST10F272Z2 Table 27. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if ...
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Central processing unit (CPU) 7.3 MAC co-processor specific instructions The Table 28 lists the MAC instructions of the ST10F272Z2. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are ...
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ST10F272Z2 8 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different ...
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Interrupt system 9 Interrupt system The interrupt response time for internal program execution is from 187 MHz CPU clock. The ST10F272Z2 architecture supports several mechanisms for fast and flexible response to service requests that ...
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ST10F272Z2 Table 29. Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 ...
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Interrupt system Table 29. Interrupt sources (continued) Source of Interrupt or PEC Service Request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC ...
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ST10F272Z2 available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits ...
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Interrupt system Table 30. X-Interrupt detailed mapping (continued) ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0 9.2 Exception and error traps list Table 31 shows all of the possible exceptions or error conditions that can arise during run- time. ...
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ST10F272Z2 10 Capture / compare (CAPCOM) units The ST10F272Z2 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125 MHz CPU clock. The ...
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Capture / compare (CAPCOM) units Table 32. Compare modes Compare Modes Interrupt-only compare mode; several compare interrupts per timer period are Mode 0 possible Pin toggles on each compare match; several compare events per timer period are Mode 1 possible ...
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ST10F272Z2 11 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The ...
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General purpose timer unit Table 35. GPT1 timer input frequencies, resolutions and periods at 40 MHz (continued MHz CPU 000b 001b Resolution 200 ns 400 ns Period 13.1 ms 26.2 ms maximum Table 36. GPT1 timer input ...
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ST10F272Z2 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock ...
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General purpose timer unit Figure 11. Block diagram of GPT2 T5EUD CPU Clock T5IN CAPIN T6IN CPU Clock T6EUD 64/189 T5 2n n=2...9 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode 2n n=2...9 Control ...
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ST10F272Z2 12 PWM modules Two pulse width modulation modules are available on ST10F272Z2: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate ...
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Parallel ports 13 Parallel ports 13.1 Introduction The ST10F272Z2 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F272Z2 has nine groups of I/O lines ...
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ST10F272Z2 13.2.2 Input threshold control The standard inputs of the ST10F272Z2 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL ...
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Parallel ports This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in ...
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ST10F272Z2 14 A/D converter A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample ...
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A/D converter register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of ...
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ST10F272Z2 15 Serial channels Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and ...
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Serial channels Table 42. ASC asynchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud Rate (Baud) Deviation Error 2 000 000 0.0% / 0.0% 112 000 +1.5% / -7.0% 56 000 +1.5% / ...
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ST10F272Z2 Table 43. ASC synchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud Rate (Baud) Deviation Error 900 0.0% / 0.0% 612 0.0% / 0.0% Table 44. ASC synchronous baud rates by reload ...
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Serial channels Table 45 and Table 46 the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8M Baud. Table 45. Synchronous baud rate and reload values (f Baud Rate Reserved ...
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ST10F272Z2 16 I2C interface 2 The integrated I C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or in multi-master mode. It can ...
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CAN modules 17 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the ...
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ST10F272Z2 Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 13. Connection to single CAN bus via separate CAN transceivers CAN_H CAN_L The ST10F272Z2 also supports single CAN ...
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CAN modules Multiple CAN bus The ST10F272Z2 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 15. Figure 15. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel Mode In ...
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ST10F272Z2 18 Real-time clock The Real-Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept ...
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Watchdog timer 19 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled ...
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ST10F272Z2 20 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 49. Reset event definition Reset ...
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System reset 20.2 Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F272Z2 is immediately (after the input filter delay) forced in reset default state. It pulls ...
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ST10F272Z2 In next Figures 17 respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter ...
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System reset Figure 17. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST 84/189 ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms ...
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ST10F272Z2 Figure 18. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST Note TCL depending on clock source selection. Hardware reset The asynchronous reset ...
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System reset Figure 19. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than ...
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ST10F272Z2 Figure 20. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500ns to take ...
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System reset Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN ...
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ST10F272Z2 Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is ...
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System reset Figure 21. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD Notes: 1. RSTIN assertion can be ...
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ST10F272Z2 Figure 22. Synchronous short / long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD Notes: 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum ...
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System reset Figure 23. Synchronous long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD Notes during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage ...
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ST10F272Z2 Figure 24. Synchronous long hardware RESET ( TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD Notes during the reset condition (RSTIN low), RPD voltage ...
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System reset Refer to next Figures 29 for bidirectional. 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and ...
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ST10F272Z2 Figure 26 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 20.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of ...
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System reset The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary Software or Watchdog Bidirectional reset event is active and RPD becomes low, the ...
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ST10F272Z2 Figure 27 WDT bidirectional RESET (EA=1) RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not ...
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System reset Figure 28 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 98/189 ≥ ≤ 500 ns not transparent not t. ...
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ST10F272Z2 Figure 29 WDT bidirectional RESET (EA=0) followed RESET RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 20.7 Reset circuitry Internal reset circuitry is described in resistor of 50 kΩ to 250 ...
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System reset To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason recommended to connect ...
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ST10F272Z2 Figure 31. System reset circuit ST10F272 Figure 32. Internal (simplified) reset circuitry Internal Reset Signal External Hardware RSTIN o.d. R0 Open Drain Inverter RPD + C0 EINIT Instruction Clr Q Set Reset State ...
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System reset 20.8 Reset application examples Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 33. Example of software or watchdog ...
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ST10F272Z2 Figure 34. Example of software or watchdog bidirectional reset ( System reset 103/189 ...
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System reset 20.9 Reset summary A summary of the different reset events is reported in the table below. Table 50. Reset event Event Asynch. Power-on Reset Asynch ...
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ST10F272Z2 Table 50. Reset event (continued) Event Synch Synch. (2) Software Reset Synch Synch Synch Synch. (2) Watchdog Reset ...
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System reset Figure 35. PORT0 bits latched into the different registers after reset H.7 H.6 CLKCFG RP0H CLKCFG Clock Generator P0L.7 ROMEN 10 9 106/189 PORT0 H.5 H.4 H.3 H.2 H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL ...
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ST10F272Z2 21 Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F272Z2. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU and ...
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Power reduction modes Before entering Power Down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set. Note: Leaving the main voltage regulator active during Power Down may lead to unexpected behavior (ex: CPU wake-up) and ...
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ST10F272Z2 In normal running mode (that is when main V during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with V oscillator used in conjunction with Real-Time ...
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Power reduction modes Warning: 21.3.2 Exiting stand-by mode After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V ...
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ST10F272Z2 21.3.4 Power reduction modes summary In the following Table 52: Power reduction modes Power reduction modes is reported. Table 52. Power reduction modes summary Mode Idle Power Down Stand- off off ...
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Programmable output clock divider 22 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is ...
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ST10F272Z2 23 Register set This section summarizes all registers implemented in the ST10F272Z2, ordered by name. 23.1 Special function registers The following table lists all SFRs which are implemented in the ST10F272Z2 in alphabetical order. Bit-addressable SFRs are marked with ...
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Register set Table 53. List of special function registers (continued) Physical Name address CC4 FE88h CC4IC b FF80h CC5 FE8Ah CC5IC b FF82h CC6 FE8Ch CC6IC b FF84h CC7 FE8Eh CC7IC b FF86h CC8 FE90h CC8IC b FF88h CC9 FE92h ...
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ST10F272Z2 Table 53. List of special function registers (continued) Physical Name address CC21 FE6Ah CC21IC b F16Ah E CC22 FE6Ch CC22IC b F16Ch E CC23 FE6Eh CC23IC b F16Eh E CC24 FE70h CC24IC b F170h E CC25 FE72h CC25IC b ...
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Register set Table 53. List of special function registers (continued) Physical Name address DP0H b F102h E DP1L b F104h E DP1H b F106h E DP2 b FFC2h DP3 b FFC6h DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h ...
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ST10F272Z2 Table 53. List of special function registers (continued) Physical Name address ODP7 b F1D2h E ODP8 b F1D6h E ONES b FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H b FF06h P2 b FFC0h P3 b ...
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Register set Table 53. List of special function registers (continued) Physical Name address PW1 FE32h PW2 FE34h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E QR0 F004h E QR1 F006h E QX0 F000h E QX1 F002h ...
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ST10F272Z2 Table 53. List of special function registers (continued) Physical Name address T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h ...
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Register set Table 53. List of special function registers (continued) Physical Name address XPERCON b F024h E ZEROS b FF1Ch Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset Value ...
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ST10F272Z2 Table 54. List of XBus registers (continued) Name CAN1IF2CR CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 ...
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Register set Table 54. List of XBus registers (continued) Name CAN2IF2A1 CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 ...
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ST10F272Z2 Table 54. List of XBus registers (continued) Name RTCDL RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 ...
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Register set Table 54. List of XBus registers (continued) Name XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB 124/189 Physical Description address ...
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ST10F272Z2 23.3 Flash registers ordered by name The following table lists all Flash Control Registers which are implemented in the ST10F272Z2 ordered by their name. These registers are physically mapped on the IBus, except for XFVTAUR0, which is mapped on ...
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... Register set IDMANUF (F07Eh / 3Fh Table 56. IDMANUF Bit Manufacturer identifier MANUF 020h: STMicroelectronics manufacturer (JTAG worldwide normalization). IDCHIP (F07Ch / 3Eh Table 57. IDCHIP Bit Device identifier IDCHIP 110h: ST10F272Z2 identifier (272). Device revision identifier REVID Xh: According to revision number. IDMEM (F07Ah / 3Dh MEMTYP R Table 58 ...
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ST10F272Z2 IDPROG (F078h / 3Ch Table 59. IDPROG Bit Programming V PROGVDD V DD following formula: V PROGVPP Programming V Note: All identification words are read only registers. The values written inside different Identification Register bits are ...
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Known limitations 24 Known limitations This section describes all functional and electrical limitations identified on the silicon revision A of the ST10F272Z2. They are listed in The revision number of the device can be read in the IDCHIP register (@F07Ch) ...
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ST10F272Z2 24.1 Injected conversion stalling the ADC Description Whenever a new injection request occurs before the ADDAT2 register has been read by the CPU (that is, when the result of the previous injection request has not been read), the ADC ...
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Known limitations not know that a new converted value is ready to be read in ADDAT2 register. Therefore at the following injection request the ADC fills the temporary register again (without generating any ADEINT interrupt request) and then the ADC ...
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ST10F272Z2 24.2 Concurrent transmission requests in DAR-mode (C-CAN module) Description When the C-CAN module is configured to operate in DAR-mode (Disable Automatic Retransmission) and the host requests the transmission of several messages at the same time, only two of these ...
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Known limitations 24.3 Transmission request disabled (C-CAN module) Description The transmission request of a message object may remain disabled (even if the host immediately enables it again) in the following situations the host disables the pending transmission request ...
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ST10F272Z2 24.4 Spurious BREQ pulse in slave mode during external bus arbitration phase Description Sporadic bus errors may occur when external bus arbitration is used via the HOLD function and the ST10F272Z2 is configured as a slave. After the slave ...
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Known limitations 24.5 Flash wake-up from idle mode Description When waking up from idle mode, the Flash response time is slower than in running mode. This can lead to an incorrect data read or code fetch when the CPU frequency ...
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ST10F272Z2 multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM. 24.7 Flash wake-up from Power Down mode Description When waking up from interruptible Power Down mode, the Flash response ...
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Known limitations 3) Load the Tx timer with the CCy register minus 1: MOV TxREL, #value MOV Tx, #( value-1) bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 136/189 ST10F272Z2 ...
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ST10F272Z2 25 Electrical characteristics 25.1 Absolute maximum ratings Table 61. Absolute maximum ratings Symbol V Voltage on V pins with respect to ground ( Voltage on V pin with respect to ground (V STBY STBY V Voltage ...
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Electrical characteristics 25.2 Recommended operating conditions Table 62. Recommended operating conditions Symbol V Operating supply voltage DD V Operating stand-by supply voltage STBY V Operating analog reference voltage AREF T Ambient temperature under bias A T Junction temperature under bias ...
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ST10F272Z2 Table 63. Thermal characteristics Symbol Thermal Resistance Junction-Ambient PQFP 144 - 3 0.65 mm pitch Θ TQFP 144 - 0.5 mm pitch JA TQFP 144 - 20 x ...
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Electrical characteristics 25.5 DC characteristics ± 10 Table 65. DC characteristics Parameter Input low voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, ...
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ST10F272Z2 Table 65. DC characteristics (continued) Parameter Output high voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTOUT) (2) Output high voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output high voltage RPD Input leakage current (P5[15:0]) Input leakage current (all ...
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Electrical characteristics Table 65. DC characteristics (continued) Parameter (11) Power Down supply current (RTC off, Oscillators off, Main Voltage Regulator off) (11) Power Down supply current (RTC on, Main Oscillator on, Main Voltage Regulator off) (11) Power Down supply current ...
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ST10F272Z2 Figure 40. Port2 test mode structure Fast external interrupt input Figure 41. Supply current versus the operating frequency (RUN and IDLE modes) 150 100 Clock Input Alternate data input latch Test mode Flash sense amplifier and ...
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Electrical characteristics 25.6 Flash characteristics = 5 V ± 10 Table 66. Flash characteristics Parameter (2) Word Program (32-bit) (2)) Double Word Program (64-bit) Bank 0 Program (256K) (Double Word Program) Sector Erase (8K) Sector Erase (32K) ...
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... Data retention time (average ambient temperature 60 °C) 256Kbyte (code store) > 20 years - - - ST10F2xx”). Contact your local field service, local sales person or STMicroelectronics Electrical characteristics (1) 64Kbyte (EEPROM emulation) > 20 years > 20 years 10 years 1 year 145/189 ...
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Electrical characteristics 25.7 A/D converter characteristics ± 10 ≤ V ≤ AGND Table 68. A/D converter characteristics Parameter Analog Reference voltage 1) Analog Ground voltage Analog Input voltage 2) Reference supply ...
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ST10F272Z2 ‘LSB’ has a value of V For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see I specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum ...
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Electrical characteristics Table 69. A/D converter programming (continued) ADCTC ADSTC Sample 11 00 TCL * 240 11 01 TCL * 280 11 10 TCL * 400 11 11 TCL * 800 10 00 TCL * 480 10 01 TCL * ...
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ST10F272Z2 Non-linearity error Non-Linearity error is the deviation between actual and the best-fitting A/D conversion characteristics (see ● Differential Non-Linearity error is the actual step dimension versus the ideal one (1 LSB ). IDEAL ● Integral Non-Linearity error is the ...
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Electrical characteristics 25.7.4 Analog reference pins The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion. A low pass filter on ...
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ST10F272Z2 Data about maximum input leakage current at each pin are provided in the Data Sheet (Electrical Characteristics section). Input leakage is greatest at high operating temperatures, and in general it decreases by one half for each 10° C decrease ...
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Electrical characteristics This relation can again be simplified considering only C condition. In reality, the transient is faster, but the A/D Converter circuitry has been designed to be robust also in the very worst case: the sampling time T longer ...
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ST10F272Z2 Figure 45. Anti-aliasing filter and conversion rate Analog Source Bandwidth ( Anti-Aliasing Filter ( The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage ...
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Electrical characteristics 1. Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 2. Using the relation between possible to define ...
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ST10F272Z2 25.8 AC characteristics 25.8.1 Test waveforms Figure 46. Input / output waveforms 2.4V 0.4V AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made at V Figure ...
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Electrical characteristics Figure 48. Generation mechanisms for the CPU clock Phase locked loop operation f XTAL f CPU Direct Clock Drive f XTAL f CPU Prescaler Operation f XTAL f CPU 25.8.3 Clock generation modes Next Table 70 associates the ...
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ST10F272Z2 25.8.4 Prescaler operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal 2:1 prescaler. The frequency of f the duration of an individual TCL) is defined ...
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Electrical characteristics an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU ...
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ST10F272Z2 Table 71. Internal PLL divider mechanism (continued) P0.15-13 XTAL (P0H.7-5) Frequency MHz 6.4 MHz MHz MHz The ...
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Electrical characteristics Jitter in the input clock PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher ...
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ST10F272Z2 Figure 49. ST10F272Z2 PLL jitter ±5 ±4 ±3 ±2 ±1 T JIT 0 0 25.8.10 PLL lock / unlock During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and ...
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Electrical characteristics Table 72. PLL characteristics (V Symbol T PLL Start-up time PSUP T PLL Lock-in time LOCK Single Period Jitter T JIT (cycle to cycle = 2 TCL) F PLL free running frequency free 1. Not 100% tested, guaranteed ...
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ST10F272Z2 Table 74. Main oscillator negative resistance (module) C min. 545 Ω 4 MHz 240 Ω 8 MHz The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the ...
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Electrical characteristics Table 76. Minimum values of negative resistance (module) for 32 kHz oscillator 32kHz - The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF to ...
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ST10F272Z2 Figure 52. External clock drive XTAL1 Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: when 64MHz is used, ...
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Electrical characteristics 25.8.16 Multiplexed bus ± 10 ALE cycle time = 6 TCL + 2t Table 79. Multiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE ...
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ST10F272Z2 Table 79. Multiplexed bus timings (continued) Symbol Parameter Latched CS low to Valid Data Latched CS hold after RD ALE fall. edge to RdCS, WrCS (with RW delay) ...
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Electrical characteristics Figure 53. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE ALE t 6 CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH 168/189 ...
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ST10F272Z2 Figure 54. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/Data Bus (P0) RD Write cycle Address/Data Bus (P0) WR WRL WRH ...
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Electrical characteristics Figure 55. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx 170/189 ...
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ST10F272Z2 Figure 56. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read cycle t 6 Address/Data Bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx ...
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Electrical characteristics 25.8.17 Demultiplexed bus ± 10 ALE cycle time = 4 TCL + 2t Table 80. Demultiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE ...
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ST10F272Z2 Table 80. Demultiplexed bus timings (continued) Symbol Parameter ALE falling edge to Latched Latched CS low to Valid Data Latched CS hold after RD Address setup to ...
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Electrical characteristics Figure 57. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 174/189 ...
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ST10F272Z2 Figure 58. External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE CLKOUT ALE t CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH t ...
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Electrical characteristics Figure 59. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 176/189 t ...
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ST10F272Z2 Figure 60. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx ...
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Electrical characteristics 25.8.18 CLKOUT and READY ± 10 Table 81. CLKOUT and READY timings Symbol Parameter t CC CLKOUT cycle time CLKOUT high time CLKOUT low time 31 ...
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ST10F272Z2 Figure 61. CLKOUT and READY CLKOUT ALE RD, WR Synchronous READY Asynchronous READY 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY ...
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Electrical characteristics 25.8.19 External bus arbitration = 5 V ± 10 Table 82. External bus arbitration timings Symbol HOLD input setup time CLKOUT CLKOUT to HLDA high BREQ low ...
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ST10F272Z2 Figure 63. External bus arbitration (regaining the bus) CLKOUT HOLD HLDA BREQ CSx (On P6.x) Other signals 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is ...
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Electrical characteristics 25.8.20 High-speed synchronous serial interface (SSC) timing 25.8.20.1 Master mode ±10 Table 83. SSC master mode timings Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time ...
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ST10F272Z2 Figure 64. SSC master timing 1) SCLK MTSR MRST 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on ...
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Electrical characteristics Table 84. SSC slave mode timings (continued) Symbol Parameter Read data setup time before latch SR edge, phase error detection off t 317 (SSCPEN = 0) Read data hold time after latch SR edge, phase error detection off ...
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ST10F272Z2 26 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Package information Figure 66. PQFP144 - 144-pin plastic quad flatpack mm, 0.65 mm pitch, package outline 109 144 Table 85. PQFP144 - 144-pin plastic quad flatpack mm, 0.65 mm pitch, package mechanical data Symbol ...
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ST10F272Z2 Figure 67. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch, package outline 108 109 b 144 1 Table 86. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch, package ...
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Revision history 27 Revision history Table 87. Document revision history Date 29-Jun-2006 11-Jan-2008 188/189 Revision 1 Initial release on www.st.com ST10F272 replaced by ST10F272Z2 Added Section 24: Known limitations on page 128 Modified example Oscillator on page ...
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... ST10F272Z2 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...