IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 

Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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Input/Output Ports (PORTS)
12.3.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each
of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRBx bit is configured as output.
Address: $000C
Bit 7
Read:
PTBPUE7
PTBPUE6
Write:
Reset:
0
Figure 12-8. Port B Input Pullup Enable Register (PTBPUE)
PTBPUE[7:0] — Port B Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port B pins
1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0
0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its
DDRB bit.
Table 12-3
summarizes the operation of the port B pins.
PTBPUE
DDRB
PTB
Bit
Bit
Bit
(1)
1
0
X
0
0
X
X
1
X
1. X = don’t care
2. I/O pin pulled to V
by internal pullup.
DD
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
102
6
5
4
3
PTBPUE5
PTBPUE4
PTBPUE3
0
0
0
0
Table 12-3. Port B Pin Functions
Accesses to DDRB
I/O Pin
Mode
Read/Write
(2)
Input, V
DDRB7–DDRB0
DD
(4)
DDRB7–DDRB0
Input, Hi-Z
Output
DDRB7–DDRB0
MC68HC908QY/QT Family Data Sheet, Rev. 6
2
1
Bit 0
PTBPUE2
PTBPUE2
PTBPUE0
0
0
0
Accesses to PTB
Read
Write
Pin
PTB7–PTB0
Pin
PTB7–PTB0
PTB7–PTB0
PTB7–PTB0
Freescale Semiconductor
(3)
(3)