IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 

Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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OSCILLATOR
OSCILLATOR
13.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four.
13.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The
IBUS clocks start upon completion of the time out.
13.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is
selectable as 4096 or 32 BUSCLKX4 cycles. See
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
13.4 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see
the resets sets a corresponding bit in the SIM reset status register (SRSR). See
Freescale Semiconductor
FROM
BUSCLKX4
SIM COUNTER
BUSCLKX2
FROM
÷
2
SIM
Figure 13-2. SIM Clock Signals
13.7.2 Stop
Mode.
13.5 SIM
Counter), but an external reset does not. Each of
MC68HC908QY/QT Family Data Sheet, Rev. 6
Reset and System Initialization
BUS CLOCK
GENERATORS
13.8 SIM
Registers.
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