MC68HC908QY1VDTE Freescale Semiconductor, MC68HC908QY1VDTE Datasheet - Page 132

IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part Number
MC68HC908QY1VDTE
Description
IC MCU 1.5K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY1VDTE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
16-TSSOP
Processor Series
HC08Q
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Timer Interface Module (TIM)
CHxMAX — Channel x Maximum Duty Cycle Bit
14.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
132
When the TOVx bit is at a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Address: $02A
Address: $0026
Address: $0027
Address: $0029
CHxMAX
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
TCHx
OVERFLOW
Figure 14-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
COMPARE
Figure 14-8
PERIOD
OUTPUT
TCH0H
TCH0L
TCH1H
TCH1L
Bit 14
Bit 14
MC68HC908QY/QT Family Data Sheet, Rev. 6
Bit 6
Bit 6
6
6
6
6
OVERFLOW
Figure 14-8. CHxMAX Latency
Bit 13
Bit 13
Bit 5
Bit 5
shows, the CHxMAX bit takes effect in the cycle after it is set
5
5
5
5
COMPARE
OUTPUT
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
OVERFLOW
Bit 12
Bit 12
Bit 4
Bit 4
4
4
4
4
COMPARE
OUTPUT
Bit 11
Bit 11
Bit 3
Bit 3
3
3
3
3
OVERFLOW
Bit 10
Bit 10
Bit 2
Bit 2
2
2
2
2
COMPARE
OUTPUT
Bit 9
Bit 1
Bit 9
Bit 1
OVERFLOW
1
1
1
1
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0

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