IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 


Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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Timer Interface Module (TIM)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
Figure 14-8
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
CHxMAX
14.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0026
TCH0H
Bit 7
Read:
Bit 15
Write:
Reset:
Address: $0027
TCH0L
Bit 7
Read:
Bit 7
Write:
Reset:
Address: $0029
TCH1H
Bit 7
Read:
Bit 15
Write:
Reset:
Address: $02A
TCH1L
Bit 7
Read:
Bit 7
Write:
Reset:
Figure 14-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
132
shows, the CHxMAX bit takes effect in the cycle after it is set
OVERFLOW
OVERFLOW
OUTPUT
OUTPUT
COMPARE
COMPARE
Figure 14-8. CHxMAX Latency
6
5
4
3
Bit 14
Bit 13
Bit 12
Bit 11
Indeterminate after reset
6
5
4
3
Bit 6
Bit 5
Bit 4
Bit 3
Indeterminate after reset
6
5
4
3
Bit 14
Bit 13
Bit 12
Bit 11
Indeterminate after reset
6
5
4
3
Bit 6
Bit 5
Bit 4
Bit 3
Indeterminate after reset
MC68HC908QY/QT Family Data Sheet, Rev. 6
OVERFLOW
OVERFLOW
OUTPUT
COMPARE
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
Freescale Semiconductor