IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 


Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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Development Support
Table 15-1. Monitor Mode Signal Requirements and Options
IRQ
RST
Reset
Mode
(PTA2)
(PTA3)
Vector
Normal
V
V
X
TST
DD
Monitor
$FFFF
V
X
DD
(blank)
Forced
Monitor
$FFFF
V
X
SS
(blank)
Not
User
X
X
$FFFF
MON08
V
RST
TST
Function
[4]
[6]
[Pin No.]
1. PTA0 must have a pullup resistor to V
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256 and baud rate using internal oscillator is bus frequency / 335.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
15.3.1.1 Normal Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as V
applied to the IRQ pin. If the IRQ pin is lowered (no longer V
monitor mode, but the pin functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register
BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.
142
Serial
Mode
Communi-
Selection
cation
COP
PTA0
PTA1 PTA4
1
1
0
Disabled
1
X
X
Disabled
1
X
X
Disabled
X
X
X
Enabled
COM
MOD0
MOD1
[8]
[12]
[10]
in monitor mode.
DD
NC
1
2
GND
NC
3
4
RST
NC
5
6
IRQ
NC
7
8
PTA0
NC
9
10
PTA4
NC
11
12
PTA1
OSC1
13
14
NC
V
15
16
NC
DD
TST
(CONFIG)) when V
was lowered. With V
TST
MC68HC908QY/QT Family Data Sheet, Rev. 6
Communication
Speed
Comments
External
Bus
Baud
Clock
Frequency
Rate
9.8304
2.4576
Provide external
9600
MHz
MHz
clock at OSC1.
9.8304
2.4576
Provide external
9600
MHz
MHz
clock at OSC1.
3.2 MHz
Internal clock
X
9600
(Trimmed)
is active.
X
X
X
OSC1
[13]
15.3.2
Security). After the
TST
) then the chip will still be operating in
lowered, the BIH and
TST
Freescale Semiconductor
is