MC68HC908QY1VDTE Freescale Semiconductor, MC68HC908QY1VDTE Datasheet - Page 145

IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part Number
MC68HC908QY1VDTE
Description
IC MCU 1.5K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY1VDTE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
16-TSSOP
Processor Series
HC08Q
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
A brief description of each monitor mode command is given in
Freescale Semiconductor
Data Returned
3
Wait one bit time after each echo before sending the next byte.
Notes:
SENT TO MONITOR
ECHO
Notes:
Description
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
WRITE
ECHO
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
ECHO
4
FROM
HOST
Operand
Opcode
FROM
HOST
READ
READ
1
WRITE
1
READ
READ
Table 15-3. READ (Read Memory) Command
Read byte from memory
2-byte address in high-byte:low-byte order
Returns contents of specified address
$4A
3
ADDRESS
MC68HC908QY/QT Family Data Sheet, Rev. 6
4
HIGH
ADDRESS
ADDRESS
Figure 15-15. Read Transaction
Figure 15-16. Write Transaction
HIGH
HIGH
1
ADDRESS
1
Command Sequence
HIGH
ADDRESS
ADDRESS
HIGH
HIGH
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
3
ADDRESS
NOTE
4
LOW
ADDRESS
ADDRESS
LOW
LOW
1
ADDRESS
1
LOW
ADDRESS
ADDRESS
LOW
LOW
Table 15-3
3
DATA
3, 2
1
through
DATA
DATA
DATA
Table
RETURN
RETURN
4
2, 3
Monitor Module (MON)
15-8.
145

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