IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 


Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 3)
Revision
Date
Level
September,
N/A
Initial release
2002
1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list.
Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages.
Figure 2-1. Memory Map — Clarified illegal address and unimplemented
memory.
Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for
Port A Data Register (PTA) and Data Direction Register A (DDRA).
Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard
interrupt and ADC conversion complete interrupt.
Chapter 13 System Integration Module (SIM) — Removed reference to break
status register as it is duplicated in break module.
11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified
oscillator trim option ordering information and what to expect with untrimmed
device.
Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected.
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) —
Diagram updated for clarity.
December,
0.1
2002
Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7,
DDRA7, and DDRA6.
Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7.
Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for
DDRA7 and DDRA6.
Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1
Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion
of auto wakeup for clarity.
Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity.
Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation.
Chapter 16 Electrical Specifications — Extensive changes made to electrical
specifications.
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case
outline drawing for DFN package.
Chapter 17 Ordering Information and Mechanical Specifications — Added
ordering information for DFN package.
January,
0.2
4.2 Features — Corrected third bulleted item.
2003
4
Description
MC68HC908QY/QT Family Data Sheet, Rev. 6
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