IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 

Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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Revision History (Sheet 2 of 3)
Revision
Date
Level
Reformatted to meet latest M68HC08 documentation standards
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt
module and TCLK pin designator.
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator.
Table 1-2. Pin Functions — Added TCLK pin description.
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to
add TCLK.
Figure 2-1. Memory Map — Corrected names for the IRQ status and control
register (INTSCR) bits 3–0.
August,
1.0
2003
3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock
prescaler bits.
4.3 Functional Description — Updated periodic wakeup request values.
Figure 6-1. COP Block Diagram — Reworked for clarity
Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF,
ACK, and IMASK
Chapter 14 Timer Interface Module (TIM) — Added TCLK function.
15.3 Monitor Module (MON) — Updated with additional data.
Chapter 16 Electrical Specifications — Updated with additional data.
Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented
areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available.
Also corrected $FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity
6.3.2 STOP Instruction — Added subsection
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity.
October,
Table 13-2. Reset Recovery Timing — Replaced previous table with new
2.0
2003
information.
Chapter 14 Timer Interface Module (TIM) — Updated with additional data.
Figure 15-3. Break I/O Register Summary — Corrected bit designators for the
BRKAR register
15.3 Monitor Module (MON) — Clarified seventh bullet.
Table 17-1. MC Order Numbers — Corrected temperature and package
designators.
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
January,
Oscillator Trim Value at $FFC0.
3.0
2004
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
Freescale Semiconductor
Description
MC68HC908QY/QT Family Data Sheet, Rev. 6
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