IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 


Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Page 71
72
Page 72
73
Page 73
74
Page 74
75
Page 75
76
Page 76
77
Page 77
78
Page 78
79
Page 79
80
Page 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Page 72/184

Download datasheet (2Mb)Embed
PrevNext
Bit Manipulation
Branch
Read-Modify-Write
DIR
DIR
REL
DIR
INH
MSB
0
1
2
3
4
LSB
5
4
3
4
1
0
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
5
4
1
BRCLR0
BCLR0
BRN
CBEQ
CBEQA
CBEQX
3
DIR
2
DIR
2
REL
3
DIR
3
IMM
3
5
4
3
5
2
BRSET1
BSET1
BHI
MUL
1
INH
1
3
DIR
2
DIR
2
REL
5
4
3
4
1
3
BRCLR1
BCLR1
BLS
COM
COMA
COMX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
4
1
4
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
4
3
5
BRCLR2
BCLR2
BCS
STHX
LDHX
LDHX
3
DIR
2
DIR
2
REL
2
DIR
3
IMM
2
5
4
3
4
1
6
BRSET3
BSET3
BNE
ROR
RORA
RORX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
4
1
7
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
4
1
8
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
4
1
9
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
4
1
A
BRSET5
BSET5
BPL
DEC
DECA
DECX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
5
3
B
BRCLR5
BCLR5
BMI
DBNZ
DBNZA
DBNZX
3
DIR
2
DIR
2
REL
3
DIR
2
INH
2
5
4
3
4
1
C
BRSET6
BSET6
BMC
INC
INCA
INCX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
3
1
D
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
5
4
3
5
E
BRSET7
BSET7
BIL
MOV
3
DIR
2
DIR
2
REL
3
DD
2 DIX+
5
4
3
3
1
F
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
3
DIR
2
DIR
2
REL
2
DIR
1
INH
1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
IMM Immediate
IX
Indexed, No Offset
SP2 Stack Pointer, 16-Bit Offset
DIR Direct
IX1
Indexed, 8-Bit Offset
IX+
Indexed, No Offset with
EXT Extended
IX2
Indexed, 16-Bit Offset
Post Increment
DD
Direct-Direct
IMD Immediate-Direct
IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct
DIX+ Direct-Indexed
Post Increment
*
Pre-byte for stack pointer indexed instructions
Table 7-2. Opcode Map
Control
INH
IX1
SP1
IX
INH
INH
IMM
5
6
9E6
7
8
9
A
1
4
5
3
7
3
NEG
NEG
NEG
RTI
BGE
SUB
INH
2
IX1
3
SP1
1
IX
1
INH
2
REL
2
4
5
6
4
4
3
CBEQ
CBEQ
CBEQ
RTS
BLT
CMP
IMM
3 IX1+
4
SP1
2
IX+
1
INH
2
REL
2
7
3
2
3
DIV
NSA
DAA
BGT
SBC
INH
1
INH
1
INH
2
REL
2
1
4
5
3
9
3
COM
COM
COM
SWI
BLE
CPX
INH
2
IX1
3
SP1
1
IX
1
INH
2
REL
2
1
4
5
3
2
2
LSR
LSR
LSR
TAP
TXS
AND
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
4
3
4
1
2
CPHX
CPHX
TPA
TSX
BIT
DIR
3
IMM
2
DIR
1
INH
1
INH
2
1
4
5
3
2
ROR
ROR
ROR
PULA
LDA
INH
2
IX1
3
SP1
1
IX
1
INH
2
1
4
5
3
2
1
ASR
ASR
ASR
PSHA
TAX
AIS
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
1
4
5
3
2
1
LSL
LSL
LSL
PULX
CLC
EOR
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
1
4
5
3
2
1
ROL
ROL
ROL
PSHX
SEC
ADC
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
1
4
5
3
2
2
DEC
DEC
DEC
PULH
CLI
ORA
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
3
5
6
4
2
2
DBNZ
DBNZ
DBNZ
PSHH
SEI
ADD
INH
3
IX1
4
SP1
2
IX
1
INH
1
INH
2
1
4
5
3
1
1
INC
INC
INC
CLRH
RSP
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
1
3
4
2
1
TST
TST
TST
NOP
BSR
INH
2
IX1
3
SP1
1
IX
1
INH
2
4
4
4
1
MOV
MOV
MOV
STOP
LDX
*
3
IMD
2 IX+D
1
INH
2
1
3
4
2
1
1
CLR
CLR
CLR
WAIT
TXA
AIX
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
Low Byte of Opcode in Hexadecimal
Register/Memory
DIR
EXT
IX2
SP2
IX1
SP1
B
C
D
9ED
E
9EE
2
3
4
4
5
3
4
SUB
SUB
SUB
SUB
SUB
SUB
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
CMP
CMP
CMP
CMP
CMP
CMP
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
SBC
SBC
SBC
SBC
SBC
SBC
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
CPX
CPX
CPX
CPX
CPX
CPX
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
AND
AND
AND
AND
AND
AND
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
BIT
BIT
BIT
BIT
BIT
BIT
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
LDA
LDA
LDA
LDA
LDA
LDA
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
STA
STA
STA
STA
STA
STA
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
EOR
EOR
EOR
EOR
EOR
EOR
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
ADC
ADC
ADC
ADC
ADC
ADC
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
ORA
ORA
ORA
ORA
ORA
ORA
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
ADD
ADD
ADD
ADD
ADD
ADD
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
3
JMP
JMP
JMP
JMP
2
DIR
3
EXT
3
IX2
2
IX1
4
4
5
6
5
JSR
JSR
JSR
JSR
REL
2
DIR
3
EXT
3
IX2
2
IX1
2
3
4
4
5
3
4
LDX
LDX
LDX
LDX
LDX
LDX
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
STX
STX
STX
STX
STX
STX
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
MSB
0
High Byte of Opcode in Hexadecimal
LSB
5
Cycles
0
BRSET0
Opcode Mnemonic
3
DIR
Number of Bytes / Addressing Mode
IX
F
2
SUB
1
IX
2
CMP
1
IX
2
SBC
1
IX
2
CPX
1
IX
2
AND
1
IX
2
BIT
1
IX
2
LDA
1
IX
2
STA
1
IX
2
EOR
1
IX
2
ADC
1
IX
2
ORA
1
IX
2
ADD
1
IX
2
JMP
1
IX
4
JSR
1
IX
2
LDX
1
IX
2
STX
1
IX