MC908JL16CSPE Freescale Semiconductor, MC908JL16CSPE Datasheet
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MC68HC908JL16 Data Sheet M68HC08 Microcontrollers MC68HC908JL16 Rev. 1.1 11/2005 freescale.com ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ...
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... Revision History Revision History Revision Date Level November, 1.1 Order part number: MC908JL16CFAE changed to MC908JL16CFJE. 2005 November, 1 First general release. 2005 4 Description MC68HC908JL16 Data Sheet, Rev. 1.1 Page Number(s) 217 N/A Freescale Semiconductor ...
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... Chapter 12 Keyboard Interrupt Module (KBI 155 Chapter 13 Computer Operating Properly (COP 161 Chapter 14 Low-Voltage Inhibit (LVI 165 Chapter 15 Central Processor Unit (CPU 167 Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 217 Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 5 ...
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... List of Chapters 6 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Map Chapter 3 (CONFIG and MOR) Chapter 4 System Integration Module (SIM) MC68HC908JL16 Data Sheet, Rev ...
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... Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6 5.4.3 Oscillator Enable Signal (SIMOSCEN 5.4.4 XTAL Oscillator Clock (XTALCLK 5.4.5 RC Oscillator Clock (RCCLK 5.4.6 Oscillator Out 2 (2OSCOUT 5.4.7 Oscillator Out (OSCOUT 5.4.8 Internal Oscillator Clock (ICLK Chapter 5 Oscillator (OSC) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 Features 7.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Freescale Semiconductor Chapter 6 Timer Interface Module (TIM) Chapter 7 MC68HC908JL16 Data Sheet, Rev. 1.1 9 ...
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... Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.8 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.9 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.10 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.11 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10 Chapter 8 Multi-Master IIC Interface (MMIIC) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.8.2 ADC10 Result High Register (ADRH 134 9.8.3 ADC10 Result Low Register (ADRL 134 9.8.4 ADC10 Clock Register (ADCLK 135 Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (ADC) MC68HC908JL16 Data Sheet, Rev. 1.1 11 ...
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... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.7 Keyboard Module During Break Interrupts 159 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12 Chapter 10 Input/Output (I/O) Ports Chapter 11 External Interrupt (IRQ) Chapter 12 Keyboard Interrupt Module (KBI) Chapter 13 Computer Operating Properly (COP) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Freescale Semiconductor Chapter 14 Low-Voltage Inhibit (LVI) Chapter 15 Central Processor Unit (CPU) MC68HC908JL16 Data Sheet, Rev. 1.1 13 ...
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... Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.5 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.6 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 17.7 5-V Oscillator Characteristics 207 17.8 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 17.9 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14 Chapter 16 Development Support Chapter 17 Electrical Specifications MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17.13 ADC10 Characteristics 212 17.14 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 17.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Ordering Information and Mechanical Specifications 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Freescale Semiconductor Chapter 18 MC68HC908JL16 Data Sheet, Rev. 1.1 15 ...
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... Table of Contents 16 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Optional low-voltage detection with reset and selectable trip points for 3-V and 5-V operation – Illegal opcode detection with reset – Illegal address detection with reset 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor (1) MC68HC908JL16 Data Sheet, Rev. 1.1 17 ...
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... Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908JL16. 18 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... LED direct sink pin 5. 25-mA output drive pin 6. Pin is open-drain output when MMIIC function enabled; position of SDA and SCL are selected in CONFIG2 register. 7. Pins available on 32-pin packages only Figure 1-1. MC68HC908JL16 Block Diagram Freescale Semiconductor INTERNAL BUS KEYBOARD INTERRUPT MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE ...
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... PTE0/T2CH0 16 17 PTE1/T2CH1 Figure 1-3. 32-Pin SDIP Pin Assignment MC68HC908JL16 Data Sheet, Rev. 1.1 24 PTD5/T1CH1 23 PTD2/ADC9 22 PTA4/KBI4 21 PTD3/ADC8 20 PTB0/ADC0 19 PTB1/ADC1 18 PTD1/ADC10 17 PTB2/ADC2 ADC12/T2CLK PTA7/KBI7 RST PTA5/KBI5 PTD4/T1CH0 PTD5/T1CH1 PTD2/ADC9 PTA4/KBI4 PTD3/ADC8 PTB0/ADC0 PTB1/ADC1 PTD1/ADC10 PTB2/ADC2 PTB3/ADC3 PTD0/ADC11 PTB4/ADC4 Freescale Semiconductor ...
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... External IRQ pin; with programmable internal pull up and Schmitt trigger input IRQ Used for monitor mode entry OSC1 Crystal or RC oscillator input OSC2: crystal oscillator output; inverted OSC1 signal OSC2/RCCLK RCCLK: RC oscillator clock output Pin as PTA6/KBI6 (see PTA0–PTA7) Freescale Semiconductor 28 RST PTA5/KBI5 3 26 PTD4/T1CH0 ...
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... DD V Input/output DD V Input DD V Input DD V Output DD V Output Input/output (open-drain Input/output (open-drain) V Input/output Input Input/output Input SS DD Output VSS V Input/output DD V Input/output DD V Output SS V Output DD V Input Input/output (open-drain Input/output (open-drain) V Input/output DD V Input/output DD V Input/output DD Freescale Semiconductor ...
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... FLASH block protect register, FLBPR (FLASH register) • $FFD0; Mask option register, MOR (FLASH register) • $FFFF; COP control register, COPCTL Freescale Semiconductor Figure 2-2, contain most of the control, status, and data registers. MC68HC908JL16 Data Sheet, Rev. 1.1 Figure 2-1, includes: ...
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... BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) RESERVED MONITOR ROM 447 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) MASK OPTION REGISTER (MOR) RESERVED 11 BYTES USER FLASH VECTORS 36 BYTES Figure 2-1. Memory Map MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Port D Control Register $000A Write: (PDCR) Reset: $000B Unimplemented Read: Data Direction Register E $000C Write: (DDRE) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset ...
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... SCTE TC SCRF IDLE Unaffected by reset SCP1 SCP0 Indeterminate = Unimplemented MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 KEYF 0 IMASKK MODEK ACKK Reserved Freescale Semiconductor ...
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... Write: High (TMODH) Reset: Read: TIM1 Counter Modulo $0024 Write: Register Low (T1MODL) Reset: Read: TIM1 Channel 0 Status and $0025 Write: Control Register (T1SC0) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit KBIE7 KBIE6 KBIE5 KBIE4 ...
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... Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 0 PS2 PS1 PS0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Reserved Freescale Semiconductor ...
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... Write: (ADRL) Reset: Read: ADC10 Clock Register $003F Write: (ADCLK) Reset: Read: Multi-Master IIC $0040 Master Control Register Write: (MIMCR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit CH0F CH0IE MS0B MS0A Bit 15 Bit 14 Bit 13 Bit 12 ...
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... IF14 IF13 IF12 IF11 Indeterminate = Unimplemented MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 MMAD3 MMAD2 MMAD1 MMEXTAD MMTXAK REPSEN MMRXAK 0 MMTXBE MMRXBF MMTD3 MMTD2 MMTD1 MMTD0 MMRD3 MMRD2 MMRD1 MMRD0 SBSW See note 0 ILAD MODRST LVI IF1 IF10 0 IF8 IF7 Reserved Freescale Semiconductor ...
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... FLASH Block Protect $FFCF Register Write: (1) (FLBPR) Reset: Read: Mask Option Register $FFD0 Write: (1) (MOR) Reset: 1. Non-volatile FLASH registers; write by programming. Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit ...
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... TIM1 channel 0 vector (low) IF2 — Not used $FFFA IRQ vector (high) IF1 $FFFB IRQ vector (low) $FFFC SWI vector (high) — $FFFD SWI vector (low) $FFFE Reset vector (high) — $FFFF Reset vector (low) MC68HC908JL16 Data Sheet, Rev. 1.1 Support.) Vector Freescale Semiconductor ...
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... Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users ...
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... This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation not selected HVEN MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 MASS ERASE PGM Freescale Semiconductor ...
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... Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Freescale Semiconductor NOTE NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 FLASH Memory ...
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... PROG Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 36 NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...
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... With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries — 64 bytes) within the FLASH memory. 38 NOTE BPR6 BPR5 BPR4 BPR3 Unaffected by reset; $FF when blank 16-bit memory address 1 1 BPR[7:0] MC68HC908JL16 Data Sheet, Rev. 1.1 , present on the IRQ pin. This voltage TST 2 1 Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... The end address of the protected range is always $FFFF. 2. $BC00–$BFFF is always protected unless entire FLASH memory is unprotected, BPR[7:0} = $FF. Freescale Semiconductor Start of Address of Protect Range The entire FLASH memory is protected. $C040 (1100 0000 0100 0000) $C080 (1100 0000 1000 0000) $C0C0 (1100 0000 1100 0000) and so on ...
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... Memory 40 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Reset: Read: Mask Option Register $FFD0 Write: (3) (MOR) Reset: 1. One-time writable register after each reset. 2. LVIT1 and LVIT0 reset power-on reset (POR) only. 3. Non-volatile FLASH register; write by programming. Figure 3-1. CONFIG Registers Summary Freescale Semiconductor – –2 ICLK cycles) Bit IRQPUD ...
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... SSREC bit. 42 NOTE Figure 3-2 and Figure 3- LVID Reserved 13 4 – ICLK cycles 18 4 – ICLK cycles Chapter 14 Low-Voltage Inhibit NOTE MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 SSREC STOP COPD Chapter 13 Computer Operating (LVI).) Freescale Semiconductor ...
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... STOP_ICLKDIS — Internal Oscillator Stop Mode Disable Bit Setting STOP_ICLKDIS disables the internal oscillator during stop mode. When this bit is cleared, the internal oscillator continues to operate in stop mode. Reset clears this bit Internal oscillator disabled during stop mode 0 = Internal oscillator enabled during stop mode Freescale Semiconductor ...
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... Bits 6–0 — Should be left as logic 1’s. When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available Unaffected by reset = Reserved Figure 3-4. Mask Option Register (MOR) NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Chapter 5 Oscillator (OSC).) 2 1 Bit Freescale Semiconductor ...
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... Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor is a summary of the SIM I/O registers. The SIM is a system state Table 4-1. Signal Name Conventions Description MC68HC908JL16 Data Sheet, Rev. 1.1 45 ...
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... ICLK (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW NOTE ILOP ILAD MODRST LVI Freescale Semiconductor Bit ...
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... CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. Freescale Semiconductor Bit 7 6 ...
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... Counter), but an external reset does not. Each of Table 4-2. PIN Bit Set Timing Number of Cycles Required to Set PIN 4163 (4096 + ( VECT H Figure 4-4. External Reset Timing MC68HC908JL16 Data Sheet, Rev. 1.1 4.7 SIM Registers.) Table 4-2 for details. VECT L Freescale Semiconductor ...
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... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. Freescale Semiconductor Reset.) Note that for POR resets, the SIM cycles through 4096 ICLK Figure 4-5 ...
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... MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. 50 4096 32 32 CYCLES CYCLES Figure 4-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908JL16 Data Sheet, Rev. 1.1 $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...
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... Break interrupts 4.5.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 4-8 flow charts the handling of system interrupts. Freescale Semiconductor 4.6.2 Stop Mode 4.3.2 Active Resets from Internal Sources MC68HC908JL16 Data Sheet, Rev. 1.1 SIM Counter ...
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... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER 1 INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO Figure 4-8. Interrupt Processing MC68HC908JL16 Data Sheet, Rev. 1.1 STACK CPU REGISTERS. SET I BIT. EXECUTE INSTRUCTION. Freescale Semiconductor ...
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... When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Freescale Semiconductor shows interrupt recovery timing. SP – – – ...
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... The interrupt status registers can be useful for debugging. 54 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 BACKGROUND ROUTINE Table 4-3 summarizes the Freescale Semiconductor ...
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... Figure 4-12. Interrupt Status Register 1 (INT1) IF1, IF3 to IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 0, 1, and 3 — Always read 0 Freescale Semiconductor Table 4-3. Interrupt Sources Flag — — IRQF ...
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... SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state IF13 IF12 IF11 IF10 Support.) The SIM puts the CPU into the break MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 0 IF8 IF7 Table 4- Bit IF15 Table 4-3. Freescale Semiconductor ...
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... IAB WAIT ADDR IDB PREVIOUS DATA R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Freescale Semiconductor WAIT ADDR + 1 SAME NEXT OPCODE Figure 4-15. Wait Mode Entry Timing MC68HC908JL16 Data Sheet, Rev. 1.1 Low-Power Modes Figure 4-15 ...
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... RST pin OR CPU interrupt OR break interrupt 32 32 Cycles Cycles $A6 NOTE Figure 4-18 NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 $00FD $00FC $6E RST VCT H RST VCT L shows stop mode entry timing. Freescale Semiconductor ...
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... This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt Freescale Semiconductor STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 4-18 ...
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... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = POR or read of RSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of RSR PIN COP ILOP ILAD MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 MODRST LVI Freescale Semiconductor ...
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... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...
Page 62
... System Integration Module (SIM) 62 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 63
... Oscillator Selection The oscillator type is selected by programming a bit in a FLASH memory location; the mask option register (MOR), at $FFD0. (See 3.5 Mask Option Register On the ROM device, the oscillator is selected by a ROM-mask layer at factory. Freescale Semiconductor (MOR).) NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 63 ...
Page 64
... Component values should have a tolerance less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: • C EXT • R EXT Unaffected by reset = Reserved Figure 5-1. Mask Option Register (MOR) NOTE Figure 5-3. MC68HC908JL16 Data Sheet, Rev. 1 Bit Freescale Semiconductor ...
Page 65
... Figure 5-2. XTAL Oscillator External Connections FROM SIM SIMOSCEN EN MCU EXT Figure 5-3. RC Oscillator External Connections Freescale Semiconductor TO SIM TO SIM 2OSCOUT OSCOUT XTALCLK ÷ 2 OSC2 can be zero (shorted) when used with higher-frequency crystals. S refer to manufacturer’s data. See Chapter 17 Electrical Specifications ...
Page 66
... RC-oscillator. 66 FROM SIM TO SIM AND COP SIMOSCEN ICLK EN INTERNAL OSCILLATOR Figure 5-4. Internal Oscillator NOTE 3.4 Configuration Register 2 (CONFIG2)). OSC2 Pin Function Inverting OSC1 Controlled by PTA6EN bit in PTAPUE ($000D) PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6/KBI6 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 67
... Oscillator During Break Mode The OSCOUT, 2OSCOUT, and ICLK clocks continue to be driven out when the device enters the break state. Freescale Semiconductor Figure 5-2 shows only the logical relation of XTALCLK to OSC1 voltage. (See Chapter 17 Electrical Specifications MC68HC908JL16 Data Sheet, Rev ...
Page 68
... Oscillator (OSC) 68 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 69
... Pin Names: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. Freescale Semiconductor Table 6-1. Pin Name Conventions T[1,2]CH0 T[1,2]CH1 ...
Page 70
... CH0F MS0A MS0B ELS0B ELS0A CH1F MS0A Figure 6-1. TIM Block Diagram NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT CH01IE LOGIC CH1IE Freescale Semiconductor ...
Page 71
... TIM2 Status and Control $0030 Register Write: (T2SC) Reset: Read: TIM2 Counter Register High $0031 Write: (T2CNTH) Reset: Read: TIM2 Counter Register $0032 Low Write: (T2CNTL) Reset: Figure 6-2. TIM I/O Register Summary (Sheet Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit ...
Page 72
... Indeterminate after reset Bit Indeterminate after reset CH1F 0 CH1IE MS1A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented MC68HC908JL16 Data Sheet, Rev. 1 Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 Freescale Semiconductor ...
Page 73
... Figure 6-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM Freescale Semiconductor NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Functional Description 6 ...
Page 74
... Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the 74 6.9.1 TIM Status and Control OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Register. OVERFLOW OUTPUT COMPARE 6.4.4 Pulse Width Freescale Semiconductor ...
Page 75
... Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. Freescale Semiconductor NOTE Table 6-3.) NOTE MC68HC908JL16 Data Sheet, Rev ...
Page 76
... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 76 Registers.) 16.2.6.4 Break Flag Control Register MC68HC908JL16 Data Sheet, Rev. 1.1 (BFCR).) Freescale Semiconductor ...
Page 77
... TIM status and control register (TSC) • TIM counter registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0, TSC1) • TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) Freescale Semiconductor Register.) The minimum T2CLK pulse width, 1 ------------------------------------ - + t SU bus frequency NOTE MC68HC908JL16 Data Sheet, Rev ...
Page 78
... Reset clears the TRST bit Prescaler and TIM counter cleared effect Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000 TOIE TSTOP TRST NOTE NOTE MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 PS2 PS1 PS0 Freescale Semiconductor ...
Page 79
... Figure 6-5. TIM Counter Registers High (TCNTH) Address: T1CNTL, $0022 and T2CNTL, $0032 Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 6-6. TIM Counter Registers Low (TCNTL) Freescale Semiconductor Table 6-2. Prescaler Selection PS1 PS0 TIM Clock Source Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ ...
Page 80
... Selects buffered or unbuffered output compare/PWM operation Address: T1SC0, $0025 and T2SC0, $0035 Bit 7 Read: CH0F Write: 0 Reset: 0 Figure 6-9. TIM Channel 0 Status and Control Register (TSC0 NOTE CH0IE MS0B MS0A ELS0B MC68HC908JL16 Data Sheet, Rev. 1 Bit Bit Bit Bit Bit 0 ELS0A TOV0 CH0MAX Freescale Semiconductor ...
Page 81
... When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 6-3. Reset clears the MSxA bit Initial output level low 0 = Initial output level high Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). Freescale Semiconductor CH1IE ...
Page 82
... CHxMAX bit takes effect in the cycle MC68HC908JL16 Data Sheet, Rev. 1.1 Configuration Capture on rising edge only Capture on falling edge only Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Freescale Semiconductor ...
Page 83
... Read: Bit 7 Write: Reset: Figure 6-13. TIM Channel 0 Register Low (TCH0L) Address: T1CH1H, $0029 and T2CH1H, $0039 Bit 7 Read: Bit 15 Write: Reset: Figure 6-14. TIM Channel 1 Register High (TCH1H) Freescale Semiconductor OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 6-11. CHxMAX Latency ...
Page 84
... Timer Interface Module (TIM) Address: T1CH1L, $002A and T2CH1L, $003A Bit 7 Read: Bit 7 Write: Reset: Figure 6-15. TIM Channel 1 Register Low (TCH1L Indeterminate after reset MC68HC908JL16 Data Sheet, Rev. 1 Bit Bit 0 Freescale Semiconductor ...
Page 85
... Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Bus clock as baud rate clock source Freescale Semiconductor NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 85 ...
Page 86
... R = Reserved Figure 7-1. SCI I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 Table 7-1 shows the full names TxD (1) PTD6/TxD/SCL WAKE ILTY PEN ILIE TE RE RWU ORIE NEIE FEIE BKF SCR2 SCR1 Unaffected Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 ...
Page 87
... SCTIE TCIE SCRIE ILIE TE SCTE RE RWU SCRF SBK WAKEUP CONTROL ÷ 4 BUS CLOCK 7.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Freescale Semiconductor INTERNAL BUS TC OR IDLE LOOPS RECEIVE CONTROL CONTROL BKF ENSCI RPF PRE- BAUD ...
Page 88
... DMATE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 7-4. SCI Transmitter MC68HC908JL16 Data Sheet, Rev. 1.1 NEXT BIT START STOP BIT BIT PARITY NEXT BIT START BIT 8 STOP BIT BIT 11-BIT TRANSMIT TxD TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE Freescale Semiconductor ...
Page 89
... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 Functional Description 89 ...
Page 90
... SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. 90 NOTE 1.) MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 91
... SCP1 SCP0 PRE- ÷ 4 BUS CLOCK SCALER BKF RPF M WAKE ILTY PEN PTY Freescale Semiconductor INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA RxD RECOVERY ALL 0s WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SCRIE DMARE OR ORIE ...
Page 92
... START BIT VERIFICATION SAMPLING Figure 7-6. Receiver Data Sampling Table 7-2. Start Bit Verification Start Bit Samples Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No MC68HC908JL16 Data Sheet, Rev. 1.1 LSB DATA Noise Flag Freescale Semiconductor ...
Page 93
... If the data recovery logic does not detect a logic 1 where the stop bit should incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. Freescale Semiconductor Table 7-3. Data Bit Recovery Data Bit ...
Page 94
... RT cycles at the point when 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 7-7, the receiver counts 170 RT cycles at the point when 170 163 – × 100 = 4.12% ------------------------- - 170 MC68HC908JL16 Data Sheet, Rev. 1.1 STOP Freescale Semiconductor ...
Page 95
... Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: Freescale Semiconductor STOP DATA SAMPLES Figure 7-8 ...
Page 96
... CPU interrupt requests. • Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. 96 NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 97
... The PTD6/TxD/SCL pin is the serial data output from the SCI transmitter. 7.7.2 RxD (Receive Data) The PTD7/RxD/SDA pin is the serial data input to the SCI receiver. Freescale Semiconductor in for information on exiting wait mode. for information on exiting stop mode. MC68HC908JL16 Data Sheet, Rev. 1.1 ...
Page 98
... This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit Transmitter output inverted 0 = Transmitter output not inverted Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits ENSCI TXINV M WAKE NOTE MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 ILTY PEN PTY Freescale Semiconductor ...
Page 99
... Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Control Bits M PEN and PTY Freescale Semiconductor Table Figure NOTE Table 7-5. Character Format Selection Character Format Start Bits Data Bits Parity 1 8 None 1 9 None 1 7 Even ...
Page 100
... This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests 100 TCIE SCRIE ILIE MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 RE RWU SBK Freescale Semiconductor ...
Page 101
... Transmit break characters break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. Freescale Semiconductor NOTE NOTE NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 ...
Page 102
... This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled 102 DMARE DMATE ORIE Unaffected CAUTION CAUTION MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 NEIE FEIE PEIE Freescale Semiconductor ...
Page 103
... SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register Freescale Semiconductor 1.) Reset clears PEIE ...
Page 104
... This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit Noise detected noise detected 104 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 105
... SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit Parity error detected parity error detected BYTE 1 READ SCS1 SCRF = 1 READ SCDR BYTE 1 Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR ...
Page 106
... Reading the SCDR accesses the read-only received data bits, R[7:0]. Writing to the SCDR writes the data to be transmitted, T[7:0]. Reset has no effect on the SCDR. Do not use read/modify/write instructions on the SCI data register. 106 Unaffected by reset Figure 7-15. SCI Data Register (SCDR) NOTE MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 BKF RPF Bit Freescale Semiconductor ...
Page 107
... SCR2, SCR1, and SCR0 Use this formula to calculate the SCI baud rate: where: SCI clock source = bus clock PD = prescaler divisor BD = baud rate divisor Table 7-8 shows the SCI baud rates that can be generated with a 4.9152 MHz bus clock. Freescale Semiconductor SCP1 SCP0 ...
Page 108
... MC68HC908JL16 Data Sheet, Rev. 1.1 Baud Rate (BUS CLOCK= 4.9152 MHz) 76,800 38,400 19,200 9,600 4,800 2,400 1,200 600 25,600 12,800 6,400 3,200 1,600 800 400 200 19,200 9,600 4,800 2,400 1,200 600 300 150 5,908 2,954 1,477 739 369 185 92 46 Freescale Semiconductor ...
Page 109
... Arbitration loss detection and No-ACK awareness in master mode • 8 selectable baud rate master clocks • Automatic recognition of the received acknowledge bit Freescale Semiconductor (CONFIG2)) to share either PTA2/PTA3 or PTD6/PTD7 based on NOTE and therefore cannot be driven to higher than DD MC68HC908JL16 Data Sheet, Rev. 1.1 ...
Page 110
... MMTXIF MMATCH MMSRW MMTD7 MMTD6 MMTD5 MMTD4 MMRD7 MMRD6 MMRD5 MMRD4 Unimplemented MC68HC908JL16 Data Sheet, Rev. 1.1 (1) ( MMRW MMBR2 MMBR1 MMAD3 MMAD2 MMAD1 MMTXAK REPSEN MMRXAK 0 MMTXBE MMTD3 MMTD2 MMTD1 MMRD3 MMRD2 MMRD1 Freescale Semiconductor Bit 0 MMBR0 0 MMEXTAD MMRXBF 0 MMTD0 1 MMRD0 0 ...
Page 111
... START signal. As shown in signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. Freescale Semiconductor LSB MSB 5 ...
Page 112
... The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. 112 8-2. There is one clock pulse on SCL for each data bit, the MSB being MC68HC908JL16 Data Sheet, Rev. 1.1 Figure 8-2). Freescale Semiconductor ...
Page 113
... There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. SCL1 SCL2 SCL Internal Counter Reset Freescale Semiconductor Delay Figure 8-3. IIC Clock Synchronization MC68HC908JL16 Data Sheet, Rev. 1.1 Functional Description Figure 8-3) ...
Page 114
... Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.6.1 Wait Mode The MMIC module remains active in wait mode. 8.6.2 Stop Mode The MMIIC module remains active in stop mode. 114 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 115
... Reset clears this bit MMIIC responds to the following calling addresses: $MMAD[7:1], 0000000, and 0001100 MMIIC responds to address $MMAD[7:1] For example, when MMADR is configured as: MMAD7 MMAD6 1 1 Freescale Semiconductor MMAD6 MMAD5 MMAD4 MMAD3 0 ...
Page 116
... The REPSEN bit is cleared by hardware after the completion of repeated START signal or when the MMAST bit is cleared. Reset clears this bit Repeated START signal will be generated if MMAST bit is set repeated START signal will be generated 116 NOTE MMIEN MMTXAK MC68HC908JL16 Data Sheet, Rev. 1.1 2 Bit Bit REPSEN Freescale Semiconductor ...
Page 117
... The MMRW bit determines the transfer direction of the data bytes that follows. When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit Master mode receive 0 = Master mode transmit Freescale Semiconductor ...
Page 118
... Internal bus clock ÷ 128 0 0 Internal bus clock ÷ 256 0 1 Internal bus clock ÷ 512 1 0 Internal bus clock ÷ 1024 MMTXIF MMATCH MMSRW MMRXAK MC68HC908JL16 Data Sheet, Rev. 1.1 Baud Rate 2 1 Bit 0 0 MMTXBE MMRXBF Freescale Semiconductor ...
Page 119
... If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be Freescale Semiconductor ...
Page 120
... MMIIC module) to release the bus, and hence clearing the MMBB flag. This is the only way to clear the MMBB flag by software if the module hangs up due STOP condition received. The MMIIC can resume operation again by setting the MMEN bit. 120 MMRD6 MMRD5 MMRD4 MMRD3 MC68HC908JL16 Data Sheet, Rev. 1.1 Figure 8-10 Bit 0 MMRD2 MMRD1 MMRD0 Figure 8-10. Freescale Semiconductor ...
Page 121
... START MMTXBE=1 MMRXBF=0 (d) Slave Receive Mode START Address MMTXBE=0 MMRXBF=0 Shaded data packets indicate transmissions by the MCU Figure 8-10. Data Transfer Sequences for Master/Slave Transmit/Receive Modes Freescale Semiconductor 0 ACK TX Data1 ACK MMTXBE=1 MMTXBE=1 MMTXIF=1 MMTXIF=1 Data2 → MMDTR Data3 → MMDTR ...
Page 122
... Multi-Master IIC Interface (MMIIC) 122 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 123
... Mode Write: (ADRH) Reset: Read: ADC10 Data Register $003E Low Write: (ADRL) Reset: Read: $003F ADC10 Clock Register Write: (ADCLK) Reset: Freescale Semiconductor and V as its supply and reference pins. This MCU uses OSCOUT DD SS Bit COCO AIEN ADCO ADCH4 ...
Page 124
... Figure 9-2. ADC10 Block Diagram REFL and V are straight-line linear conversions. REFL NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 ASYNC ACLKEN CLOCK GENERATOR ACLK BUS CLOCK ALTERNATE CLOCK SOURCE 1 AIEN INTERRUPT 2 COCO and ADVIN is equal to REFH REFL , the converter circuit converts it to $000. Freescale Semiconductor ...
Page 125
... A conversion is completed when the result of the conversion is transferred into the data result registers, ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is high at the time that COCO is set. Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 Functional Description ...
Page 126
... MC68HC908JL16 Data Sheet, Rev. 1.1 Table 9-1. Maximum Conversion Time 18 ADCK + 3 bus clock 18 ADCK + 3 bus clock + 5 µs 16 ADCK 38 ADCK + 3 bus clock 38 ADCK + 3 bus clock + 5 µs 36 ADCK 21 ADCK + 3 bus clock 21 ADCK + 3 bus clock + 5 µs 19 ADCK 41 ADCK + 3 bus clock 41 ADCK + 3 bus clock + 5 µs 39 ADCK Freescale Semiconductor ...
Page 127
... SSA REFL • The MCU is placed in wait mode immediately after initiating the conversion (next instruction after write to ADCSC). • There is no I/O switching, input or output, on the MCU during the conversion. Freescale Semiconductor 21 ADCK cycles 3 bus cycles + 16 MHz/8 NOTE minimum and f ADCK ...
Page 128
... As a consequence, LSB LSB ). Note, if the last conversion is $3FE, then the LSB MC68HC908JL16 Data Sheet, Rev. 1 (if available). This will REFL SSA , one-time error. LSB and the code width of the last ($FF ). Note, if the first LSB LSB ) is used. LSB Freescale Semiconductor ) is ...
Page 129
... ADCO in the ADC10 status and Control Register before executing the STOP instruction. In single conversion mode the ADC10 automatically enters a low-power state when the conversion is complete not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state. Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 Interrupts ...
Page 130
... This should be the only ground connection between SSA pin makes a good single point ground location. SSA ) REFH . If externally available, V DDA ). DDA MC68HC908JL16 Data Sheet, Rev. 1.1 is connected internally DDA . External filtering DD is connected internally SSA . SS may be connected to the same REFH DDA Freescale Semiconductor spec and ...
Page 131
... Address: $003C Bit 7 Read: COCO Write: Reset Unimplemented Figure 9-3. ADC10 Status and Control Register (ADCSC) Freescale Semiconductor NOTE and V REFH and must be placed as close as possible to the package pins. REFL ) REFL . If externally available, connect the V SSA pin to the same potential as V ...
Page 132
... It is not necessary to set the channel select bits to all 1s to place the ADC10 in a low-power state, however, because the module is automatically placed in a low-power state when a conversion completes. 132 Table 9-2. MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 133
... ADCH3 Accuracy is guaranteed for conversions on the selected channel only if V specified range any unused or reserved channels are selected, the resulting conversion will be unknown. 3. Requires LVI to be powered (LVID = 0 in CONFIG1). Freescale Semiconductor Table 9-2. Input Channel Select ADCH2 ADCH1 ADCH0 Continuing to: ...
Page 134
... In 8-bit mode, there is no interlocking with ADRH. Address: $003E Bit 7 Read: AD7 Write: R Reset Figure 9-6. ADC10 Data Register Low (ADRL) 134 Reserved Reserved AD6 AD5 AD4 AD3 Reserved MC68HC908JL16 Data Sheet, Rev. 1 Bit Bit 0 0 AD9 AD8 Bit 0 AD2 AD1 AD0 Freescale Semiconductor ...
Page 135
... This rounding process sets the transfer function to transition at the midpoint between the ideal code voltages, causing a quantization error of 1/2 . LSB Reset returns 8-bit mode. MODE1 MODE0 Freescale Semiconductor ADIV1 ADIV0 ADICLK MODE1 Table 9-3. ADC10 Clock Divide Ratio ADIV0 Divide Ratio (ADIV) ...
Page 136
... The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion The ADICLK bit specifies the input clock source and conversions will not continue in stop mode 136 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 137
... Twenty six (26) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable as inputs or outputs. Connect any unused I/O pins to an appropriate logic level, either Although the I/O ports do not require termination for proper operation, SS termination reduces excess current consumption and the possibility of electrostatic damage. Freescale Semiconductor NOTE MC68HC908JL16 Data Sheet, Rev. 1 137 ...
Page 138
... PTB1 Unaffected by reset PTD4 PTD3 PTD2 PTD1 Unaffected by reset DDRA3 DDRA2 DDRA1 DDRB3 DDRB2 DDRB1 DDRD3 DDRD2 DDRD1 PTE1 Unaffected by reset 0 SLOWD7 SLOWD6 PTDPU7 DDRE1 PTAPUE3 PTAPUE2 PTAPUE1 Freescale Semiconductor Bit 0 PTA0 PTB0 PTD0 DDRA0 0 DDRB0 0 DDRD0 0 PTE0 PTDPU6 0 DDRE0 0 PTAPUE0 0 0 ...
Page 139
... PTAPUE register has priority control over the port pin. RCCLK/PTA6/KBI6 is the OSC2 pin when OSCSEL=1 (XTAL option ESCI module is enabled (ENSCI = 1), the ESCI will have priority over the PTD6/PTD7 pins regardless of the state of the MMIIC module. Freescale Semiconductor Module Control Module Register ...
Page 140
... Chapter 12 Keyboard Interrupt Module MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 PTA3 PTA2 PTA1 PTA0 LED LED LED LED (Sink) (Sink) (Sink) (Sink) pull-up pull-up pull-up pull-up Keyboard Keyboard Keyboard Keyboard Interrupt Interrupt Interrupt Interrupt SCL SDA (KBI). 3.4Configuration Register 2 Freescale Semiconductor Chapter Chapter 8 ...
Page 141
... When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor NOTE 6 ...
Page 142
... PTA Bit I/O Pin Mode Read/Write (2) (1) DDRA[7:0] Input (4) X DDRA[7:0] Input, Hi-Z X Output DDRA[7: PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 MC68HC908JL16 Data Sheet, Rev. 1.1 Accesses to DDRA to PTA Read Write (3) Pin PTA[7:0] (3) Pin PTA[7:0] PTA[7:0] PTA[7: Bit 0 PTAPUE2 PTAPUE1 PTAPUE0 Bit Freescale Semiconductor ...
Page 143
... Figure 10-8. Data Direction Register B (DDRB) DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input Freescale Semiconductor (ADC)). PTB6 ...
Page 144
... MMIIC module (MMIIC)). PTD6 and PTD7 each has high current sink (25mA) MC68HC908JL16 Data Sheet, Rev. 1.1 Figure 10-9 shows the PTBX TO ANALOG-TO-DIGITAL CONVERTER Accesses to PTB Read Write (3) Pin PTB[7:0] PTB[7:0] PTB[7:0] Freescale Semiconductor ...
Page 145
... SDA and SCL — MMIIC Module Pins The MMIIC pins can be configured to use PTD6 and PTD7 as IIC communication pins, see Chapter 8 Multi-Master IIC Interface using CONFIG2 option bit, to allow PTD6/PTD7 to be MMIIC pins (see Register 2 (CONFIG2)). Freescale Semiconductor PTD6 PTD5 PTD4 ...
Page 146
... The data latch can always be written, regardless of the state of its data direction bit. 146 DDRD6 DDRD5 DDRD4 DDRD3 NOTE DDRDX RESET PTDX Figure 10-12. Port D I/O Circuit MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 DDRD2 DDRD1 DDRD0 Figure 10-12 shows the PTDPU[6:7] PTDX TO ADC, TIM1, SCI Freescale Semiconductor ...
Page 147
... Port E Port 2-bit special function port that shares its pins with the timer 2 interface module (see Timer Interface Module (TIM)). PTE0–PTE1 are available on 32-pin packages only. Freescale Semiconductor Table 10-4. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write ...
Page 148
... Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from port E I/O logic. 148 Unaffected by reset = Unimplemented Chapter 6 Timer Interface Module NOTE MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 PTE1 PTE0 T2CH1 T2CH0 (TIM Bit 0 DDRE1 DDRE0 Figure 10-16 shows the Freescale Semiconductor ...
Page 149
... don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. Freescale Semiconductor DDREX RESET PTEX Figure 10-16. Port E I/O Circuit Table 10-5 summarizes the operation of the port E pins. Table 10-5. Port E Pin Functions Accesses to DDRE ...
Page 150
... Input/Output (I/O) Ports 150 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 151
... When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic one Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 Figure 11-1 shows the 151 ...
Page 152
... Figure 11-1. IRQ Module Block Diagram Bit Unimplemented Figure 11-2. IRQ I/O Register Summary MC68HC908JL16 Data Sheet, Rev. 1.1 4.5 Exception TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ SYNCHRONIZER INTERRUPT REQUEST HIGH TO MODE SELECT VOLTAGE DETECT LOGIC IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...
Page 153
... To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. Freescale Semiconductor NOTE NOTE is connected to the IRQ pin ...
Page 154
... IRQPUD — IRQ Pin Pull-Up Disable Bit IRQPUD disconnects the internal pull-up on the IRQ pin Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and V 154 IRQF Unimplemented LVIT1 LVIT0 Reserved U = Unaffected MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 IMASK MODE ACK Bit Freescale Semiconductor ...
Page 155
... The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 12-1. The generic pin name appear in the text that follows. KBI Generic Pin Name KBI0–KBI5 KBI6 KBI7 1. PTA6/KBI6 is only available when OSCSEL=0 at $FFD0 (RC option), and PTA6EN=1 at $000D. Freescale Semiconductor Bit ...
Page 156
... ACKK V DD RESET CLR KEYBOARD INTERRUPT FF MODEK Registers). A logic 0 applied to an enabled keyboard interrupt pin MC68HC908JL16 Data Sheet, Rev. 1.1 INTERNAL BUS VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST IMASKK Freescale Semiconductor ...
Page 157
... Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 12.5 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: • Keyboard status and control register • Keyboard interrupt enable register Freescale Semiconductor NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Keyboard Interrupt Registers 157 ...
Page 158
... The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 Read: KBIE7 Write: Reset: 0 Figure 12-4. Keyboard Interrupt Enable Register (KBIER) 158 KEYF Unimplemented KBIE6 KBIE5 KBIE4 KBIE3 MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 0 IMASKK MODEK ACKK Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 159
... To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 Low-Power Modes ...
Page 160
... Keyboard Interrupt Module (KBI) 160 MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 161
... RESET VECTOR FETCH COPCTL WRITE COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) Freescale Semiconductor SIM 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 13-1. COP Block Diagram MC68HC908JL16 Data Sheet, Rev ...
Page 162
... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1 (CONFIG1). (See Chapter 3 Configuration and Mask Option Registers (CONFIG and 162 NOTE (RSR).). NOTE Figure 13-1. for ICLK parameters. 13.4 COP Control MC68HC908JL16 Data Sheet, Rev. 1.1 Register) clears the COP MOR).) Freescale Semiconductor ...
Page 163
... Figure 13-3. COP Control Register (COPCTL) 13.5 Interrupts The COP does not generate CPU interrupt requests. 13.6 Monitor Mode The COP is disabled in monitor mode when V 13.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Freescale Semiconductor ...
Page 164
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 13.8 COP Module During Break Mode The COP is disabled during a break interrupt when V 164 is present on the RST pin. TST MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 165
... The LVI module generates one output signal: LVI Reset — an reset signal will be generated to reset the CPU when V point LOW DETECTOR LVIT1 LVIT0 Freescale Semiconductor voltage falls to the LVI trip (LVI DD > LVI = 0 TRIP DD < LVI = 1 TRIP DD Figure 14-1. LVI Module Block Diagram MC68HC908JL16 Data Sheet, Rev ...
Page 166
... LVI module will come into action. LVIT1 and LVIT0 DD Table 14-1. Trip Voltage Selection LVIT0 Comments For For For Chapter 17 Electrical Specifications for full parameters. MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 STOP_ R R ICLKDIS Bit 0 SSREC STOP COPD ( operation operation operation DD Reserved Freescale Semiconductor ...
Page 167
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 15.3 CPU Registers Figure 15-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 167 ...
Page 168
... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 15-1. CPU Registers Unaffected by reset Figure 15-2. Accumulator ( Figure 15-3. Index Register (H:X) MC68HC908JL16 Data Sheet, Rev. 1 Bit 0 Bit Freescale Semiconductor ...
Page 169
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...
Page 170
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result 170 NOTE MC68HC908JL16 Data Sheet, Rev. 1 Bit Freescale Semiconductor ...
Page 171
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 Arithmetic/Logic Unit (ALU) ...
Page 172
... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...
Page 173
... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...
Page 174
... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...
Page 175
... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...
Page 176
... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...
Page 177
... M Memory location N Negative bit 15.8 Opcode Map See Table 15-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 178
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 179
... CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 16-1 shows the structure of the break module. Freescale Semiconductor MC68HC908JL16 Data Sheet, Rev. 1.1 179 ...
Page 180
... Bit7 Bit6 Bit5 BRKE BRKA Unimplemented 16.2.6.4 Break Flag Control Register (BFCR) MC68HC908JL16 Data Sheet, Rev. 1.1 CONTROL BKPT (TO SIM SBSW See note Bit12 Bit11 Bit10 Bit9 Bit4 Bit3 Bit2 Bit1 Reserved and see the Break Freescale Semiconductor Bit Bit8 0 Bit0 ...
Page 181
... This read/write status and control bit is set when a break address match occurs. Writing a logic one to BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit Break address match break address match Freescale Semiconductor is present on the RST pin. TST 6 5 ...
Page 182
... Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU break state. 182 Writing a logic zero clears SBSW. MC68HC908JL16 Data Sheet, Rev. 1 Bit Bit Bit Bit Bit 0 SBSW R R (1) Note 0 Freescale Semiconductor ...
Page 183
... If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see logic zero to it. 16.2.7.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 4.7 SIM Registers. Freescale Semiconductor ...
Page 184
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 184 , as long as vector addresses $FFFE and $FFFF are TST ( reset vector is blank ($FFFE and $FFFF contain TST , is applied to IRQ TST MC68HC908JL16 Data Sheet, Rev. 1.1 Figure 16-8 shows a example Freescale Semiconductor ...
Page 185
... SW2: Position C — Bus clock = OSC1 ÷ 4 SW2: Position D — Bus clock = OSC1 ÷ See Table 17-4 for V voltage level requirements. TST Freescale Semiconductor V DD EXT OSC (50% DUTY) EXT OSC CONNECTION TO OSC1, WITH OSC2 UNCONNECTED, CAN REPLACE XTAL CIRCUIT. 9.8304MHz 20 pF ...
Page 186
... PTB0. COP disabled. Blank reset vector (low-voltage) entry to monitor 2.4576MHz mode. 9600 baud communication on PTB0. COP disabled. OSC1 ÷ 4 Enters User mode. (Table 16-1 condition set 1), the bus applied to IRQ upon TST is applied to either IRQ or TST Freescale Semiconductor ...
Page 187
... Table 16-2. Monitor Mode Vector Differences Modes COP User Enabled Monitor Disabled Notes the high voltage (V COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. Freescale Semiconductor POR RESET NO IS VECTOR BLANK? YES MONITOR MODE EXECUTE MONITOR CODE NO ...
Page 188
... MC68HC908JL16 Data Sheet, Rev. 1.1 Baud Rate 9600 bps 9600 bps 4800 bps 9600 bps 4800 bps NEXT START STOP BIT BIT 7 BIT NEXT START STOP BIT BIT 7 BIT STOP NEXT BIT BIT 7 START BIT ADDR. LOW DATA RESULT Freescale Semiconductor ...
Page 189
... Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ECHO Freescale Semiconductor TWO-STOP-BIT DELAY BEFORE ZERO ECHO Figure 16-13. Break Transaction ADDR. HIGH ADDR. HIGH ADDR. LOW MC68HC908JL16 Data Sheet, Rev. 1.1 ...
Page 190
... MONITOR IWRITE IWRITE ECHO A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. 190 ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA RESULT DATA DATA NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 DATA DATA Freescale Semiconductor ...
Page 191
... If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Improved security function denies monitor mode entry if five or more of the eight security bytes are $00 (zero bytes). Freescale Semiconductor SP HIGH SP LOW RESULT ...
Page 192
... Six of the eight routines are intended to simplify FLASH program, erase, and load operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM. Table 16-10 shows a summary of the ROM-resident routines. 192 NOTE 4096 + 32 ICLK CYCLES 24 BUS CYCLES MC68HC908JL16 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 193
... During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. FILE_PTR ADDRESS AS POINTER Figure 16-15. Data Block Format for ROM-Resident Routines Freescale Semiconductor Routine Description Program a range of locations Erase a page or the entire array Loads data from a range of locations monitor mode from bytes at a time ...
Page 194
... Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Data Block Format Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN) ; Indicates 4x bus frequency ; Data size to be programmed ; FLASH start address ; Reserved data array MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 195
... PRGRNGE (see ERARNGE EQU $FCBE MAIN: BSR INITIALISATION : : LDHX #FILE_PTR Freescale Semiconductor Table 16-12. ERARNGE Routine Routine Name ERARNGE Erase a page or the entire array Calling Address $FCBE Stack Used 7 bytes Bus speed (BUS_SPD) Data size (DATASIZE) ...
Page 196
... LDRNGE : 196 Table 16-13. LDRNGE Routine Routine Name LDRNGE Loads data from a range of locations $FF30 Stack Used 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N MC68HC908JL16 Data Sheet, Rev. 1.1 16.3.9.1 PRGRNGE). Freescale Semiconductor ...
Page 197
... The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as the ERARNGE routine (see 16.3.9.2 program via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the monitor code. Freescale Semiconductor Table 16-14. MON_PRGRNGE Routine MON_PRGRNGE Program a range of locations, in monitor mode $FC28 ...
Page 198
... LDRNGE), except that MON_LDRNGE returns to the main program via Table 16-17. EE_WRITE Routine EE_WRITE Emulated EEPROM write. Data size ranges from bytes at a time. $FD3F 24 bytes Bus speed (BUS_SPD) (1) Data size (DATASIZE) (2) Starting address (ADDRH) (1) Starting address (ADDRL) Data 1 : Data N MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 199
... The coding example below uses the $EF00–$EE3F page for data storage. The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. Freescale Semiconductor 16-16). F ...
Page 200
... The user must ensure that data size is same as the previous operation whenever this routine is executed. 200 ; Indicates 4x bus frequency ; Data size to be programmed ; FLASH page start address ; Reserved data array NOTE MC68HC908JL16 Data Sheet, Rev. 1.1 Freescale Semiconductor ...