MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 207

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.9 I/O Signals
11.9.1 TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK)
11.9.2 TIM Channel I/O Pins (PTB2/T1CH0, PTB3/T1CH1, PTB4/T2CH0, PTB5/T2CH1)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Port B shares four of its pins with the TIM channel I/O pins: T1CH0,
T1CH1, T2CH0, and T2CH1.
Port D shares two of its pins with the TIM clock input pins: T1CLK and
T2CLK
T[1,2]CLK is an external clock input that can be the clock source for the
TIM[1,2] counter instead of the prescaled internal bus clock. Select the
T[1,2]CLK input by writing logic 1’s to the three prescaler select bits,
PS[2:0]. (See
T[1,2]CLK pulse width, T[1,2]CLK
The maximum T[1,2]CLK frequency is:
T1CLK and T2CLK are available as standard I/Os or KBI pins when not
used as the TIM clock inputs.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
Timer Interface Module (TIM)
11.10.1 TIM Status and Control
------------------------------------ -
bus frequency
bus frequency ÷ 2
1
LMIN
or T[1,2]CLK
+
t
SU
Register.) The minimum
Timer Interface Module (TIM)
HMIN
, is:
Data Sheet
I/O Signals
207