MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 321

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5 Multi-Master IIC Registers
15.5.1 Multi-Master IIC Address Register (MMADR)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Addr.
$006C
$006D
$006A
$006B
$006E
$006F
Multi-Master IIC Address
Master Control Register
Multi-Master IIC Control
Data Transmit Register
Data Receive Register
Register Name
Multi-Master IIC
Multi-Master IIC
Multi-Master IIC
Multi-Master IIC
Status Register
(MMADR)
(MMDRR)
(MMDTR)
(MIMCR)
(MMCR)
Register
Register
(MMSR)
Address:
Six registers are associated with the Multi-master IIC module, they are
outlined in the following sections.
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Figure 15-1. MMIIC I/O Register Summary
Read: MMALIF MMNAKIF
Read:
Read:
Read: MMRXIF
Read:
Read: MMRD7
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 15-2. Multi-Master IIC Address Register (MMADR)
MMAD7
MMAD7
MMTD7
MMEN
$006B
Bit 7
Bit 7
Multi-Master IIC Interface (MMIIC)
0
0
1
0
0
0
1
0
1
= Unimplemented
MMTXIF MMATCH MMSRW MMRXAK
MMAD6
MMRD6
MMAD6
MMTD6
MMIEN
6
0
0
0
0
0
0
1
0
6
0
MMRD5
MMAD5
MMTD5
MMAD5
MMBB
5
0
1
0
0
0
1
0
5
1
MMRD4
MMAST
MMAD4
MMTD4
MMAD4
4
0
0
0
0
0
1
0
4
0
MMTXAK REPSEN
MMAD3
MMTD3
MMRD3
MMAD3
MMRW
3
0
0
0
1
1
0
3
0
Multi-Master IIC Interface (MMIIC)
MMBR2
MMAD2
MMRD2
MMAD2
MMTD2
Multi-Master IIC Registers
2
0
0
0
0
0
1
0
2
0
MMTXBE MMRXBF
MMBR1
MMAD1 MMEXTAD
MMRD1
MMAD1 MMEXTAD
MMTD1
1
0
0
0
0
1
1
0
1
0
Data Sheet
MMRD0
MMBR0
MMTD0
Bit 0
Bit 0
0
0
0
0
0
1
0
0
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