MC908LJ24CPKE Freescale Semiconductor, MC908LJ24CPKE Datasheet - Page 115

• Manufacturer Part Number: MC908LJ24CPKE
• Description: IC MCU 8BIT 24K FLASH 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPKE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 48
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
frequency, f
factor, E, or (L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
programmable modulo reference divider, which divides f
factor, R. The divider’s output is the final reference clock, CGMRDV,
running at a frequency, f
(30kHz–100kHz), always set R = 1 for specified performance. With an
external high-frequency clock source, use R to divide the external
frequency to between 30kHz and 100kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
fed back through a programmable pre-scaler divider and a
programmable modulo divider. The pre-scaler divides the VCO clock by
a power-of-two factor P (the CGMPCLK) and the modulo divider reduces
the VCO clock by a factor, N. The dividers’ output is the VCO feedback
clock, CGMVDV, running at a frequency, f
8.4.6 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGMXFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
condition based on this comparison.
Clock Generator Module (CGM)
RDV
NOM
8.4.4 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock
, (38.4 kHz) times a linear factor, L, and a power-of-two
E
)f
NOM
RDV
.
VRS
= f
for more information.)
RCLK
is equal to the nominal center-of-range
RCLK
/R. With an external crystal
, and is fed to the PLL through a
VDV
Clock Generator Module (CGM)
Modes. The value of the
= f
VCLK
Functional Description
/(N × 2
RCLK
P
by a
). (See
VCLK
Data Sheet
VRS
.
, is
115