MC908LJ24CPKE Freescale Semiconductor, MC908LJ24CPKE Datasheet - Page 169

• Manufacturer Part Number: MC908LJ24CPKE
• Description: IC MCU 8BIT 24K FLASH 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPKE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 48
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, V
IRQ must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these
conditions:
The second condition states that as long as V
IRQ pin after entering monitor mode, or if V
the initial reset to get into monitor mode (when V
then the COP will be disabled. In the latter situation, after V
to the RST pin, V
freeing the IRQ for normal functionality in monitor mode.
Figure 10-2
the reset vector is blank and just 1 x V
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four.
Enter monitor mode with pin configuration shown in
pulling RST low and then high. The rising edge of RST latches monitor
mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See
break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
•
•
If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ or RST.
If monitor mode was entered with V
then the COP is disabled as long as V
or RST.
10.5
shows a simplified diagram of the monitor mode entry when
Monitor ROM (MON)
TST
Security.) After the security bytes, the MCU sends a
can be removed from the IRQ pin in the interest of
DD
voltage is applied to the IRQ
TST
TST
TST
on IRQ (condition set 1),
TST
TST
is applied to RST after
is applied to either IRQ
is maintained on the
was applied to IRQ),
Figure 10-1
Functional Description
Monitor ROM (MON)
TST
is applied
Data Sheet
TST
by
, to
169