C8051F023-GQ Silicon Laboratories Inc, C8051F023-GQ Datasheet - Page 221

• Manufacturer Part Number: C8051F023-GQ
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F023-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F020DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 8-ch x 10-bit
• On-chip Dac: 2-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1200 - DEV KIT FOR F020/F021/F022/F023
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1203

C8051F020/1/2/3
21.3. Frame and Transmission Error Detection
Frame error detection is available in the following modes when the SSTAT1 bit in register PCON is set to logic 1.
Note: The SSTAT1 bit must be logic 1 to access any of the status bits (FE1, RXOVR1, and TXCOL1). To access the
UART1 Mode Select bits (SM01, SM11, and SM21), the SSTAT1 bit must be logic 0.
All Modes:
The Transmit Collision bit (TXCOL1 bit in register SCON1) reads ‘1’ if user software writes data to the SBUF1 reg-
ister while a transmit is in progress. Note that the TXCOL1 bit also functions as the SM21 bit when the SSTAT1 bit in
register PCON is logic 0.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOVR1 in register SCON1) reads ‘1’ if a new data byte is latched into the receive buffer
before software has read the previous byte. Note that the RXOVR1 bit also functions as the SM11 bit when the
SSTAT1 bit in register PCON is logic 0.
The Frame Error bit (FE1 in register SCON1) reads ‘1’ if an invalid (low) STOP bit is detected. Note that the FE1 bit
also functions as the SM01 bit when the SSTAT1 bit in register PCON is logic 0.
Rev. 1.4
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