IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part NumberHD6417041AVF16V
DescriptionIC SUPERH MCU ROMLESS 144QFP
ManufacturerRenesas Electronics America
SeriesSuperH® SH7040
HD6417041AVF16V datasheets
 


Specifications of HD6417041AVF16V

Core ProcessorSH-2Core Size32-Bit
Speed28.7MHzConnectivityEBI/EMI, SCI
PeripheralsDMA, POR, PWM, WDTNumber Of I /o98
Program Memory TypeROMlessRam Size4K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-20°C ~ 75°C
Package / Case144-QFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
Page 1/531

Download datasheet (3Mb)Embed
Next
To our customers,
Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website:
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
http://www.renesas.com
st
April 1
, 2010
Renesas Electronics Corporation

HD6417041AVF16V Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    SH-1/SH-2/SH-DSP 32 Software Manual Renesas 32-Bit RISC Microcomputer SuperH The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the ...

  • Page 4

    Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

  • Page 5

    The SH-1 and SH-2 incorporates a RISC (Reduced Instruction Set Computer) type CPU. A basic instruction can be executed in one clock cycle, realizing high performance operation. A built-in multiplier can execute multiplication and addition as quickly as DSP. The ...

  • Page 6

    Rev. 5.00 Jun 30, 2004 page iv of xiv REJ09B0171-0500O ...

  • Page 7

    Main Revisions for this Edition Item Page All Revision (See Manual for Details) All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” Rev. ...

  • Page 8

    Rev. 5.00 Jun 30, 2004 page vi of xiv REJ09B0171-0500O ...

  • Page 9

    Section 1 Features ................................................................................................................ 1.1 SH-1 and SH-2 Features.................................................................................................... 1.2 SH-DSP Features .............................................................................................................. Section 2 Register Configuration 2.1 General Registers .............................................................................................................. 2.2 Control Registers............................................................................................................... 2.3 System Registers ............................................................................................................... 11 2.4 DSP Registers ................................................................................................................... 12 2.5 Precautions for Handling of Guard ...

  • Page 10

    Instructions and Operands.................................................................................... 52 4.7.3 DC Bit.................................................................................................................. 53 4.7.4 Condition Bits ...................................................................................................... 55 4.7.5 Overflow Prevention Function (Saturation Operation) ........................................ 56 4.8 ALU Integer Operations.................................................................................................... 56 4.9 ALU Logical Operations................................................................................................... 58 4.9.1 Function ............................................................................................................... 58 4.9.2 Instructions and Operands.................................................................................... ...

  • Page 11

    Shift Instructions.................................................................................................. 103 5.1.5 Branch Instructions .............................................................................................. 104 5.1.6 System Control Instructions................................................................................. 105 5.1.7 CPU Instructions That Support DSP Functions ................................................... 108 5.2 DSP Data Transfer Instruction Set .................................................................................... 111 5.2.1 Double Data Transfer Instructions (X Memory Data) ......................................... ...

  • Page 12

    EXTS (Extend as Signed): Arithmetic Instruction............................................... 171 6.1.24 EXTU (Extend as Unsigned): Arithmetic Instruction.......................................... 173 6.1.25 JMP (Jump): Branch Instruction .......................................................................... 174 6.1.26 JSR (Jump to Subroutine): Branch Instruction (Class: Delayed Branch Instruction)........................................................................................................... 175 6.1.27 LDC (Load to Control ...

  • Page 13

    SHLRn (Shift Logical Right n Bits): Shift Instruction......................................... 242 6.1.61 SLEEP (Sleep): System Control Instruction ........................................................ 244 6.1.62 STC (Store Control Register): System Control Instruction (Interrupt Disabled Instruction)............................................................................ 245 6.1.63 STS (Store System Register): System Control Instruction (Interrupt Disabled ...

  • Page 14

    PINC (Increment by 1 with Condition): DSP Arithmetic Operation Instruction ............................................................................................................ 342 6.3.12 [if cc] PLDS (Load System Register): DSP System Control Instruction............. 347 6.3.13 PMULS (Multiply Signed by Signed): DSP Arithmetic Operation Instruction... 352 6.3.14 [if ...

  • Page 15

    Appendix A CPU Instructions A.1 CPU Instructions ............................................................................................................... 501 ......................................................................................... 501 Rev. 5.00 Jun 30, 2004 page xiii of xiv REJ09B0171-0500O ...

  • Page 16

    Rev. 5.00 Jun 30, 2004 page xiv of xiv REJ09B0171-0500O ...

  • Page 17

    SH-1 and SH-2 Features The SH-1 and SH-2 CPU have RISC-type instruction sets. Basic instructions are executed in one clock cycle, which dramatically improves instruction execution speed. The CPU also has an internal 32-bit architecture for enhanced data processing ...

  • Page 18

    Section 1 Features Item Feature Processing states Power-down states Note: * The normal minimum number of execution cycles (The number in parentheses in the number in contention with preceding/following instructions). 1.2 SH-DSP Features The SH-DSP is a 32-bit microcontroller based ...

  • Page 19

    Table 1.2 Features of SH-DSP Series Microprocessor CPUs Feature Description DSP unit DSP registers DSP data b1us Parallel processing Address operator DSP data addressing modes Repeat control Instruction set Pipeline 1 cycle multiplier 16 bits 16 bits 32 bits (fixed ...

  • Page 20

    Section 1 Features Rev. 5.00 Jun 30, 2004 page 4 of 512 REJ09B0171-0500O ...

  • Page 21

    Section 2 Register Configuration The register set of the SH-1 and SH-2 consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. The SH-DSP maintains upward compatibility with the SH-1 and SH-2 microprocessors on the ...

  • Page 22

    Section 2 Register Configuration 31 Notes functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. ...

  • Page 23

    Notes functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a source register or destination register. 2. Used as memory address register ...

  • Page 24

    Section 2 Register Configuration As0: .REG (R4); defined when an alias is needed for a single data transfer. As1: .REG (R5); defined when an alias is needed for a single data transfer. As2: .REG (R2); defined when an alias is ...

  • Page 25

    The SH-SDP additionally has a repeat start (RS) register, a repeat end (RE) register, and a modulo (MOD) register. The RS and RE registers are used to control program repetition (loops). The number of iterations is specified in the SR ...

  • Page 26

    Section 2 Register Configuration Table 2.1 SR Register Bits Bits Name 27–16 Repeat counter (RC) 11 Specification of modulo addressing for Y pointer (DMY) 10 Specification of modulo addressing for X pointer (DMX) 9 Bit M 8 Bit Q 7–4 ...

  • Page 27

    The following instructions set addresses in the RS, RE registers for zero overhead repeat control: LDRS @(disp, PC); disp LDRE @(disp, PC); disp The GBR and VBR registers are the same as the previous SuperH registers. Four control bits (DMX, ...

  • Page 28

    Section 2 Register Configuration In addition, the SH-DSP also uses as its system registers the DSP status register (DSR) and five of the eight data registers (A0, X0, X1, Y0, Y1), which are all registers of the DSP unit and ...

  • Page 29

    A0G A1G CS[2:0] DC Figure 2.6 Organization of the DSP Registers Section 2 Register Configuration 0 A0 DSP data registers ...

  • Page 30

    Section 2 Register Configuration Table 2.2 DSR Register Bits Bits Name 31–8 Reserved 7 Signed greater than bit (GT) 6 Zero value bit (Z) 5 Negative value bit (N) 4 Overflow bit (V) 3–1 Condition select bits (CS) 0 DSP ...

  • Page 31

    Initial Values of Registers Table 2.3 lists the values of the registers after reset. Table 2.3 Initial Values of Registers Classification Register General registers R0–R14 R15 (SP) Control registers GBR VBR MOD System registers MACH, MACL, ...

  • Page 32

    Section 2 Register Configuration Rev. 5.00 Jun 30, 2004 page 16 of 512 REJ09B0171-0500O ...

  • Page 33

    Section 3 Data Formats 3.1 Data Format in Registers Register operands are always longwords (32 bits). When data in memory is loaded to a register and the memory operand is only a byte (8 bits word (16 bits), ...

  • Page 34

    Section 3 Data Formats Address 2n Address 4n Figure 3.3 Data Format in Memory (Little Endian) 3.3 Immediate Data Format Byte immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is ...

  • Page 35

    The DSP type logical data format has no decimal point. The data format and valid data length vary with the instruction and DSP register. Figure 3.4 shows the three DSP data formats and the position of the two binary decimal ...

  • Page 36

    Section 3 Data Formats 3.5 DSP Instructions and Data Formats The data format and valid data length varies with the instruction and DSP register. Instructions that access the DSP data register fall into three categories: DSP data processing, X and ...

  • Page 37

    In single data transfers, the A0G and A1G registers can be handled as independent registers. Eight bits of data can be loaded to or stored from the A0G and A1G registers. When the A0G or A1G register is the source ...

  • Page 38

    Section 3 Data Formats Table 3.1 Data Format of DSP Instruction Source Register Register Instruction A0, A1 DSP operation Data transfer A0G, A1G Data transfer X0, X1, Y0, DSP Y1, M0, M1 operation Data transfer Note: * The sign is ...

  • Page 39

    Table 3.2 Data Format of DSP Instruction Destination Register Register Instruction A0, A1 DSP operation Data transfer A0G, A1G Data transfer X0, X1, Y0, DSP Y1, M0, M1 operation Data transfer Guard Bits 39–32 Fixed (Sign extend) decimal, PSHA, PMULS ...

  • Page 40

    Section 3 Data Formats 8 bits [7:0] MOVX.W, MOVY.W MOVS.W, MOVS A0G A1G DSR 7 0 Figure 3.5 Relationship between DSP Registers and Buses during Data Transfer Rev. 5.00 Jun 30, 2004 page 24 of 512 REJ09B0171-0500O 32 ...

  • Page 41

    Section 4 Instruction Features 4.1 RISC-Type Instruction Set All instructions are RISC type. Their features are detailed in this section. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program coding efficiency. One Instruction/Cycle: Basic instructions can be executed ...

  • Page 42

    Section 4 Instruction Features Table 4.2 Delayed Branch Instructions SH-1/SH-2/SH-DSP CPU BRA TRGET ADD R1,R0 Multiplication/Accumulation Operation: SH-1 CPU: 16bit 16bit 32-bit multiplication operations are executed in one to three cycles. 16bit 16bit + 42bit 42-bit multiplication/accumulation operations are executed ...

  • Page 43

    Table 4.4 Immediate Data Accessing Classification SH-1/SH-2/SH-DSP CPU 8-bit immediate MOV 16-bit immediate MOV.W ................. .DATA.W 32-bit immediate MOV.L ................. .DATA.L Note: The address of the immediate data is accessed by @(disp, PC). Absolute Address: When data is accessed by ...

  • Page 44

    Section 4 Instruction Features 4.2 Addressing Modes Addressing modes effective address calculation by the CPU core are described below. Table 4.7 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Addresses Calculation Direct Rn The effective address is register ...

  • Page 45

    Addressing Instruction Mode Format Effective Addresses Calculation Indirect @(disp:4, The effective address is Rn plus a 4-bit displacement register Rn) (disp). The value of disp is zero-extended, and addressing remains the same for a byte operation, is doubled for with ...

  • Page 46

    Section 4 Instruction Features Addressing Instruction Mode Format Effective Addresses Calculation PC relative @(disp:8, The effective address is the PC value plus an 8-bit addressing PC) displacement (disp). The value of disp is zero- with extended, and disp is doubled ...

  • Page 47

    Addressing Instruction Mode Format Effective Addresses Calculation PC relative Rn* The effective address is the register PC plus Rn. addressing (cont) Immediate #imm:8 The 8-bit immediate data (imm) for the TST, AND, addressing OR, and XOR instructions are zero-extended. #imm:8 ...

  • Page 48

    Section 4 Instruction Features Table 4.8 Instruction Formats Instruction Formats 0 format 15 xxxx xxxx xxxx xxxx n format 15 xxxx nnnn xxxx xxxx m format 15 xxxx mmmm xxxx xxxx Rev. 5.00 Jun 30, 2004 page 32 of 512 ...

  • Page 49

    Instruction Formats nm format 15 xxxx nnnn mmmm xxxx md format 15 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx nnnn dddd Note multiply/accumulate instructions, nnnn is the source register. Source Destination Operand Operand mmmm: Direct nnnn: ...

  • Page 50

    Section 4 Instruction Features Instruction Formats nmd format 15 xxxx nnnn mmmm dddd d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx i ...

  • Page 51

    DSP DSP operations and data transfers are listed below: ALU Fixed Decimal Point Operations: These are fixed decimal point operations with either 40- bit (with guard bits) or 32-bit (with no guard bits) fixed decimal point data. These include ...

  • Page 52

    Section 4 Instruction Features arithmetic shifts, and logical shifts. or MSB detection instructions and rounding instructions, set the condition bits like for arithmetic operations. Arithmetic operations include overflow preventing instructions (saturation operations). When saturation operation is specified with the S ...

  • Page 53

    X and Y Data Addressing The DSP command allows X and Y data memories to be accessed simultaneously using the MOVX.W and MOVY.W instructions. DSP instructions have two pointers so they can access the X and Y data memories ...

  • Page 54

    Section 4 Instruction Features R8[Ix] +2 (INC) +0 (No update) ALU Notes: 1. Adder added for DSP processing 2. All three addressing methods (increment, index register addition (Ix, Iy), and no update) are post-increment methods. To decrement the address pointer, ...

  • Page 55

    Note: There are four addressing methods (no update, index register addition (Is), increment, and decrement). Index register addition and increment are post-increment methods. Decrement is a pre-decrement method. Figure 4.2 Single Data Transfer ...

  • Page 56

    Section 4 Instruction Features MOV.L ModAddr,Rn; LDC Rn,MOD; ModAddr: .DATA.W mEnd; .DATA.W mStart; ModStart: .DATA : ModEnd: .DATA Set the start and end addresses in MS and ME and then set the DMX or DMY bit to 1. The address ...

  • Page 57

    R4: H'C008 Inc. R4: H'C00A Inc. R4: H'C00C (Becomes the modulo start address when the modulo end address is Inc. R4: H'C008 reached) Place data so the top 16 bits of the modulo start and end address are the same, ...

  • Page 58

    Section 4 Instruction Features As=As+(+ R8[Is] or +0); /* Inc.Index,Not-Update */ else { /* Decrement, Pre-update */ /* As is one of R2–5 */ As=As+(–2 or –4); MAB=As /* memory access cycle uses MAB. The address to ...

  • Page 59

    Instruction Formats for DSP Instructions New instructions have been added to the SH-DSP for use in digital signal processing. The new instructions are divided into two groups. Double and single data transfer instructions for memory and DSP registers (16 ...

  • Page 60

    Section 4 Instruction Features Table 4.10 Instruction Formats for Double Data Transfers Category Mnemonic X memory data NOPX transfers MOVX.W @Ax,Dx MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory data NOPY transfers MOVY.W @Ay,Dy MOVY.W @Ay+,Dy ...

  • Page 61

    Table 4.11 Instruction Formats for Single Data Transfers Category Mnemonic Single data MOVS.W @–As,Ds transfer MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@A–s MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @–As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@A–s MOVS.L ...

  • Page 62

    Section 4 Instruction Features 4.6.2 Parallel Processing Instructions Parallel processing instructions are used by the SH-DSP to increase the execution efficiency of digital signal processing using the DSP unit. They are 32 bits long and four can be processed in ...

  • Page 63

    Table 4.12 Field A Parallel Data Transfer Instructions Category Mnemonic X memory NOPX data MOVX.W @Ax,Dx transfers MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data MOVY.W @Ay,Dy transfers MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay ...

  • Page 64

    Section 4 Instruction Features Category Mnemonic PSHL #imm, Dz imm. shift PSHA #imm, Dz Reserved PMULS Se, Sf, Dg Six Reserved operand parallel instruction PSUB Sx, Sy, Du PMULS Se, Sf, Dg PADD Sx, Sy, Du PMULS Se, Sf, Dg ...

  • Page 65

    A B Category Mnemonic 1 (if cc)* PSHL Sx, Sy, Dz Conditional (if cc) PSHA Sx, Sy, Dz three (if cc) PSUB Sx, Sy, Dz operand (if cc) PADD Sx, Sy, Dz instructions Reserved (if cc) PAND Sx, Sy, Dz ...

  • Page 66

    Section 4 Instruction Features 4.7 ALU Fixed Decimal Point Operations 4.7.1 Function ALU fixed decimal point operations basically work with a 32-bit unit to which 8 guard bits are added for a total of 40 bits. When the source operand ...

  • Page 67

    Guard bits 31 Source 1 Guard bits Figure 4.6 ALU Fixed Decimal Point Operation Flowchart When the memory read destination operand is the same as the ALU operation source operand and the data transfer instruction program is written on the ...

  • Page 68

    Section 4 Instruction Features 4.7.2 Instructions and Operands Table 4.13 shows the types of ALU fixed decimal point arithmetic operations. Table 4.14 shows the correspondence between the operands and registers. Table 4.13 Types of ALU Fixed Decimal Point Arithmetic Operations ...

  • Page 69

    DC Bit The DC bit is set as follows depending on the specification of the CS0-CS2 bits (condition select bits) of the DSR register. Carry/Borrow Mode: CS2–CS0 = 000: The DC bit indicates whether a carry or borrow has ...

  • Page 70

    Section 4 Instruction Features Example 1: Negative Guard bits 1100 0000 0000 0000 0000 0000 +) 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Sign bit Figure 4.9 Distinguishing Negative and Positive Zero Mode: CS2–CS0 = ...

  • Page 71

    GT. The equation shown below defines the DC bit in this mode. However, VR becomes a positive value when the result including the guard bit area exceeds the display range of the destination operand. DC bit ...

  • Page 72

    Section 4 Instruction Features 4.7.5 Overflow Prevention Function (Saturation Operation) When the S bit of the SR register is set to 1, the overflow prevention function is engaged for the ALU fixed decimal point arithmetic operation executed by the DSP ...

  • Page 73

    Guard bits 31 Source 1 Destination Guard bits Figure 4.11 ALU Integer Operation Flowchart Table 4.15 lists the types of ALU integer operations. Table 4.16 shows the correspondence between the operands and registers. Table 4.15 Types of ALU Integer Operations ...

  • Page 74

    Section 4 Instruction Features When the S bit of the SR register is set to 1, the overflow prevention function (saturation operation) is engaged. The overflow prevention function can be specified for ALU integer arithmetic operations executed by the DSP ...

  • Page 75

    Instructions and Operands Table 4.17 lists the types of ALU logical arithmetic operations. Table 4.18 shows the correspondence between the operands and registers, which is the same as for ALU fixed decimal point operations. Table 4.17 Types of ALU ...

  • Page 76

    Section 4 Instruction Features 4.9.4 Condition Bits The condition bits are set as follows. The N bit is the value of bit 31 of the operation result. The Z bit is 1 when the operation result is zero; otherwise, the ...

  • Page 77

    Guard bits 31 Guard bits Figure 4.13 Fixed Decimal Point Multiplication Flowchart Table 4.19 shows the fixed decimal point multiplication instruction. Table 4.20 shows the correspondence between the operands and registers. Table 4.19 Fixed Decimal Point Multiplication Mnemonic Function PMULS ...

  • Page 78

    Section 4 Instruction Features The overflow prevention function is valid for DSP unit multiplication. Specify it by setting the S bit of the SR register is set to 1. When an overflow or underflow occurs, the operation result value is ...

  • Page 79

    Arithmetic Shift Operations Function: ALU arithmetic shift operations basically work with a 32-bit unit to which 8 guard bits are added for a total of 40 bits. ALU fixed decimal point operations are basically performed between registers. When the ...

  • Page 80

    Section 4 Instruction Features DC Bit: The DC bit is set as follows depending on the mode specified by the CS bits: Carry/Borrow Mode: CS2–CS0 = 000: The DC bit is the operation result, the value of the bit pushed ...

  • Page 81

    DSP stage (the last stage) of the pipeline. Whenever a logical shift operation is executed, the DSR register’s DC and GT bits ...

  • Page 82

    Section 4 Instruction Features Signed Greater Than Mode: CS2–CS0 = 100: The DC bit is always 0. In this mode, the DC bit has the same value as bit GT. Signed Greater Than Or Equal To Mode: CS2–CS0 = 101: ...

  • Page 83

    Guard bits 31 Source Priority encoder Destination 31 Guard bits Figure 4.16 MSB Detection Flowchart Section 4 Instruction Features DSR 0 : Cleared to 0 Rev. 5.00 Jun 30, 2004 page ...

  • Page 84

    Section 4 Instruction Features Table 4.23 Relationship between Source Data and Destination Data Guard Bits 7g 6g 5g– — — — — ...

  • Page 85

    Guard Bits 7g–0g 31–22 all 0 all 0 all 0 all 0 all 1 all 1 all 1 all 1 all 1 all 1 all 0 all 0 all 0 all 0 Note: * Don’t care bits have no effect. ...

  • Page 86

    Section 4 Instruction Features 4.12.2 Instructions and Operands Table 4.24 shows the MSB detection instruction. The correspondence between the operands and registers is the same as for ALU fixed decimal point operations shown in table 4.25. Table 4.24 ...

  • Page 87

    Condition Bits The condition bits are set as follows. The N bit is the same as the result of the ALU integer operation set to 1 for a negative operation result and 0 for a positive operation ...

  • Page 88

    Section 4 Instruction Features Guard bits 31 Source Destination Guard bits Rounding result H'000002 H'000001 Figure 4.18 Rounding Process Definitions Rev. 5.00 Jun 30, 2004 page 72 of 512 REJ09B0171-0500O 0 H'00008000 Addition ALU 31 0 Figure ...

  • Page 89

    Instructions and Operands Table 4.26 shows the instruction. The correspondence between the operands and registers is the same as for ALU fixed decimal point operations shown in table 4.27. Table 4.26 Rounding Instruction Mnemonic Function PRND Rounding ...

  • Page 90

    Section 4 Instruction Features 4.13.4 Condition Bits The condition bits are set as follows. They are updated as for ALU fixed decimal point arithmetic operations. The N bit is the same as the result of the ALU fixed decimal point ...

  • Page 91

    Table 4.28 Condition Select Bits (CS) and DSP Condition Bit (DC) CS Bits Condition Mode Carry/borrow Negative Zero Overflow Signed greater than ...

  • Page 92

    Section 4 Instruction Features 4.15 Overflow Prevention Function (Saturation Operation) The overflow prevention function (saturation operation) is specified by the S bit of the SR register. This function is valid for arithmetic operations executed by the DSP unit and multiply ...

  • Page 93

    Data Transfers The SH-DSP can perform up to two data transfers in parallel between the DSP register and on- chip memory with the DSP unit. The SH-DSP has the following types of data transfers and Y memory ...

  • Page 94

    Section 4 Instruction Features (16 bits). Data is transferred from the top word of the source register. Data is transferred to the top word of the destination register and the bottom word is automatically cleared with zeros. Specifying a conditional ...

  • Page 95

    The guard bit registers A0G and A1G can be specified for operands as independent registers. Single data transfers use the IAB and IDB buses in place of the X bus and Y bus, so contention occurs on the IDB bus ...

  • Page 96

    Section 4 Instruction Features Figure 4.21 Single Data Transfer Flowchart (Longword) Data transfers are executed in the MA stage of the pipeline while DSP operations are executed in the DSP stage. Since the next data store ...

  • Page 97

    PADD X0, Y0, A0 Slot 1 MOVX, IF ADD MOVX MOVX Figure 4.22 Example of the Execution of Operation and Data Store Instructions 4.17 Operand Contention Data contention occurs when the same register is specified as the destination operand for ...

  • Page 98

    Section 4 Instruction Features Table 4.32 Operand and Register Combinations That Create Contention Operation Operand X memory load memory load 6-operand ALU Sx operation Sy Du 3-operand Se multiplication Sf Dg 3-operand ALU ...

  • Page 99

    DSP Repeat (Loop) Control The SH-DSP repeat (loop) control function is a special utility for controlling repetition efficiently. The SETRC instruction is executed to hold a repeat count in the repeat counter (RC, 12 bits) and set an execution ...

  • Page 100

    Section 4 Instruction Features RptEnd: instr5; instr6; There are several restrictions on repeat control least one instruction must come between the SETRC instruction and the first instruction of the repeat program (loop). 2. Execute the SETRC instruction after ...

  • Page 101

    When there are three or fewer instructions in the loop, PC relative instructions (MOVA (disp,PC), R0, or the like) can only be used at the first instruction (instr1 there are four or more instructions in the loop, ...

  • Page 102

    Section 4 Instruction Features A: All interruption and bus error exceptions are accepted. B: Only the bus error exception is accepted interruption and bus error exceptions are accepted. When RC>=1 1-step repeat A instr0 B Start(End): instr1 C ...

  • Page 103

    Table 4.35 RS and RE Setup Rule Register 1 RS Repeat_start0+8 RE Repeat_start0+4 An example of an actual repeat program (loop) assuming various cases based on the above table is given below: Case 1: One repeat instruction LDRS RptStart0+8;(RptStart) LDRE ...

  • Page 104

    Section 4 Instruction Features Case 3: Three repeat instructions LDRS RptStart0+4;(RptStart) LDRE RptStart0+4;(RptEnd) SETRC RptCount; ---- RptStart0:instr0; RtpStart: instr1; Repeat instruction 1 instr2; Repeat instruction 2 RptEnd: instr3; Repeat instruction 3 instr4; Case 4: Four or more instructions LDRS RptStart; ...

  • Page 105

    Note 2. Extension instruction REPEAT The extension instruction REPEAT can simplify the delicate handling of the labeling and offset described in table 4.34 and Note 1. Labels used are shown below. RptStart: RptStart: Address of first instruction of repeat program ...

  • Page 106

    Section 4 Instruction Features Case 4: Four or more instructions REPEAT RptStart, RptStart, RptCount ---- instr0; RtpStart: instr1; Repeat instruction 1 instr2; Repeat instruction 2 instr3; Repeat instruction 3 ----------------------------------------- instrN-3; Repeat instruction N-3 instrN-2; Repeat instruction N-2 instrN-1; Repeat ...

  • Page 107

    Conditional Instructions and Data Transfers Data operation instructions include both unconditional and conditional instructions. Data transfer instructions that execute both in parallel can be specified, but they will always execute regardless of whether the condition is met without affecting ...

  • Page 108

    Section 4 Instruction Features Rev. 5.00 Jun 30, 2004 page 92 of 512 REJ09B0171-0500O ...

  • Page 109

    Section 5 Instruction Set The SH-DSP instructions are divided into three groups. CPU instructions are executed by the CPU core, and DSP data transfer instructions and DSP operation instructions are executed by the DSP unit. Some CPU instructions support DSP ...

  • Page 110

    Section 5 Instruction Set Operation Classification Types Code Arithmetic EXTU operations MAC (cont) MUL MULS MULU NEG NEGC SUB SUBC SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTCL ROTCR ROTL ROTR SHAL SHAR SHLL SHLLn ...

  • Page 111

    Operation Classification Types Code Branch BRA BRAF BSR BSRF JMP JSR RTS System 14 CLRMAC control CLRT LDC LDRE LDRS LDS NOP RTE SETRC SETT SLEEP STC STS TRAPA Total: 65 Instruction codes, operation, and execution cycles ...

  • Page 112

    Section 5 Instruction Set Table 5.2 Instruction Code Format Item Format Instruction OP.Sz SRC,DEST mnemonic Instruction code MSB LSB Operation , summary (xx) M/Q/T & <<n, >>n Execution cycles Instruction execution cycles T bit —: No change ...

  • Page 113

    Data Transfer Instructions Table 5.3 Data Transfer Instructions Instruction Operation imm MOV #imm,Rn @(disp,PC),Rn (disp MOV.W extension @(disp,PC),Rn (disp MOV.L Rm MOV Rm,Rn Rm MOV.B Rm,@Rn Rm MOV.W Rm,@Rn Rm MOV.L Rm,@Rn (Rm) MOV.B @Rm,Rn (Rm) MOV.W @Rm,Rn (Rm) ...

  • Page 114

    Section 5 Instruction Set Instruction Operation Rm MOV.B Rm,@(R0,Rn) Rm MOV.W Rm,@(R0,Rn) Rm MOV.L Rm,@(R0,Rn) (R0 + Rm) MOV.B @(R0,Rm),Rn (R0 + Rm) MOV.W @(R0,Rm),Rn (R0 + Rm) MOV.L @(R0,Rm),Rn R0 MOV.B R0,@(disp, GBR) R0 MOV.W R0,@(disp, GBR) R0 MOV.L ...

  • Page 115

    Arithmetic Instructions Table 5.4 Arithmetic Instructions Instruction Operation ADD Rm, imm ADD #imm, ADDC Rm,Rn Carry ADDV Rm,Rn Overflow If R0 CMP/EQ #imm, ...

  • Page 116

    Section 5 Instruction Set Instruction Operation MSB of Rn DIV0S Rm, DIV0U Signed operation of DMULS.L Rm, Unsigned operation of DMULU.L Rm, – byte sign- ...

  • Page 117

    Instruction Operation 0–Rm NEG Rm,Rn 0–Rm–T NEGC Rm,Rn Borrow Rn–Rm SUB Rm,Rn Rn–Rm–T SUBC Rm,Rn Borrow Rn–Rm SUBV Rm,Rn Underflow Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there ...

  • Page 118

    Section 5 Instruction Set 5.1.3 Logic Operation Instructions Table 5.5 Logic Operation Instructions Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) NOT Rm,Rn OR Rm,Rn OR #imm,R0 OR.B #imm,@(R0,GBR) TAS.B @Rn TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) XOR Rm,Rn XOR #imm,R0 ...

  • Page 119

    Shift Instructions Table 5.6 Shift Instructions Instruction Operation T Rn ROTL Rn LSB ROTR ROTCL ROTCR SHAL Rn MSB SHAR SHLL SHLR Rn Rn ...

  • Page 120

    Section 5 Instruction Set 5.1.5 Branch Instructions Table 5.7 Branch Instructions Instruction Operation disp BF label nop (where label is disp + PC) Delayed branch BF/S label PC PC Delayed branch ...

  • Page 121

    System Control Instructions Table 5.8 System Control Instructions Instruction Operation 0 MACH,MACL CLRMAC 0 T CLRT Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm MOD LDC Rm,MOD Rm RE LDC Rm, LDC ...

  • Page 122

    Section 5 Instruction Set Instruction Operation (Rm) PR,Rm+4 Rm LDS.L @Rm+,PR (Rm) DSR,Rm+4 Rm LDS.L @Rm+,DSR LDS.L @Rm+,A0 (Rm) A0,Rm+4 Rm (Rm) X0,Rm+4 Rm LDS.L @Rm+,X0 (Rm) X1,Rm+4 Rm LDS.L @Rm+,X1 (Rm) Y0,Rm+4 Rm LDS.L @Rm+,Y0 (Rm) Y1,Rm+4 Rm LDS.L ...

  • Page 123

    Instruction Operation DSR Rn STS DSR, STS A0, STS X0, STS X1, STS Y0, STS Y1,Rn Rn–4 Rn,MACH (Rn) STS.L MACH,@-Rn Rn–4 Rn,MACL (Rn) STS.L MACL,@-Rn Rn–4 Rn,PR (Rn) STS.L ...

  • Page 124

    Section 5 Instruction Set 5.1.7 CPU Instructions That Support DSP Functions Several system control instructions have been added to the CPU core instructions to support DSP functions. The RS, RE, and MOD registers (which support modulo addressing) have been added, ...

  • Page 125

    Table 5.9 Added CPU Instructions Instruction Operation Rm MOD LDC Rm,MOD Rm RE LDC Rm, LDC Rm,RS (Rm) MOD LDC.L @Rm+,MOD (Rm LDC.L @Rm+,RE (Rm LDC.L @Rm+,RS ...

  • Page 126

    Section 5 Instruction Set Instruction Operation Rn– (Rn) STS.L X1,@- STS Y0,Rn Rn– (Rn) STS.L Y0,@- STS Y1,Rn Rn– (Rn) STS.L Y1,@-Rn Rm[11:0] RC (SR[27:16]) SETRC Rm repeat flag imm ...

  • Page 127

    DSP Data Transfer Instruction Set Table 5.10 shows the DSP data transfer instructions by category. Table 5.10 DSP Data Transfer Instruction Categories Instruction Category Types Double data transfer 4 instructions Single data transfer 1 instructions Total 5 The data ...

  • Page 128

    Section 5 Instruction Set 5.2.1 Double Data Transfer Instructions (X Memory Data) Table 5.11 Double Data Transfer Instructions (X Memory Data) Instruction Operation No Operation NOPX (Ax) MSW of Dx,0 LSW of MOVX.W Dx @Ax,Dx (Ax) MSW of Dx,0 LSW ...

  • Page 129

    Single Data Transfer Instructions Table 5.13 Single Data Transfer Instructions Instruction Operation As–2 As,(As) MSW of MOVS.W Ds,0 LSW of Ds @-As,Ds (As) MSW of Ds,0 LSW of MOVS.W @As,Ds Ds (As) MSW of Ds,0 LSW of MOVS.W @As+,Ds ...

  • Page 130

    Section 5 Instruction Set Table 5.14 lists the correspondence between DSP data transfer operands and registers. CPU core registers are used as pointer addresses to indicate memory addresses. Table 5.14 Correspondence between DSP Data Transfer Operands and Registers Oper- R2 ...

  • Page 131

    DSP Operation Instruction Set DSP operation instructions are digital signal processing instructions that are processed by the DSP unit. Their instruction code is 32 bits long. Multiple instructions can be processed in parallel. The instruction code is divided into ...

  • Page 132

    Section 5 Instruction Set Table 5.16 Correspondence between DSP Operation Instruction Operands and Registers ALU and BPU Instructions Register Yes — A1 Yes — M0 — Yes M1 — Yes X0 Yes — X1 Yes — Y0 ...

  • Page 133

    Table 5.17 DSP Operation Instruction Categories Classification ALU ALU fixed decimal arithmetic point operation operation instructions instructions ALU integer operation instructions MSB detection instruction Rounding operation instruction ALU logical operation instructions Fixed decimal point multiplication instruction Shift Arithmetic shift operation ...

  • Page 134

    Section 5 Instruction Set 5.3.1 ALU Arithmetic Operation Instructions Table 5.18 ALU Fixed Decimal Point Operation Instructions Instruction Operation If Sx 0,Sx Dz PABS Sx,Dz If Sx<0,0– 0,Sy Dz PABS Sy,Dz If Sy<0,0–Sy Dz Sx+Sy Dz ...

  • Page 135

    Instruction Operation if DC=1, 0,nop DCT PCOPY Sy,Dz if DC=0, 1,nop DCF PCOPY Sx,Dz if DC=0, 1,nop DCF PCOPY Sy,Dz 0–Sx Dz PNEG Sx,Dz 0–Sy Dz PNEG Sy,Dz if DC=1,0–Sx Dz DCT PNEG Sx,Dz ...

  • Page 136

    Section 5 Instruction Set Table 5.19 ALU Integer Operation Instructions Instruction Operation MSW of Sx – 1 PDEC Sx,Dz clear LSW of Dz MSW of Sy – 1 PDEC Sy,Dz clear LSW DC=1, MSW of Sx – ...

  • Page 137

    Table 5.20 MSB Detection Instructions Instruction Operation Sx data MSB position PDMSB Sx,Dz of Dz, clear LSW data MSB position PDMSB Sy,Dz of Dz, clear LSW DC=1, Sx data MSB position DCT PDMSB Sx,Dz ...

  • Page 138

    Section 5 Instruction Set 5.3.2 ALU Logical Operation Instructions Table 5.22 ALU Logical Operation Instructions Instruction Operation Sx & Sy PAND Sx,Sy, DC=1, Sx & Sy DCT PAND LSW of Dz nop Sx,Sy,Dz If DC=0, Sx ...

  • Page 139

    Shift Operation Instructions Table 5.24 Arithmetic Shift Instructions Instruction Operation if Sy 0,Sx<<Sy Dz PSHA Sx,Sy,Dz if Sy<0,Sx>> DC=1 & Sy 0,Sx<<Sy Dz DCT PSHA Sx,Sy,Dz if DC=1 & Sy<0,Sx>> DC=0,nop if DC=0 & Sy ...

  • Page 140

    Section 5 Instruction Set 5.3.5 System Control Instructions Table 5.26 System Control Instructions Instruction Operation Dz MACH PLDS Dz,MACH Dz MACL PLDS Dz,MACL if DC=1,Dz MACH DCT PLDS Dz,MACH if 0,nop if DC=1,Dz MACL DCT PLDS Dz,MACL if 0,nop if ...

  • Page 141

    NOPX and NOPY Instruction Code When there is no data transfer instruction to be processed in parallel with the DSP operation instruction, a NOPX or NOPY instruction can be written as the data transfer instruction or the instruction can ...

  • Page 142

    Section 5 Instruction Set Rev. 5.00 Jun 30, 2004 page 126 of 512 REJ09B0171-0500O ...

  • Page 143

    Section 6 Instruction Descriptions 6.1 Instruction Descriptions Instructions are described in alphabetical order in three sections: CPU instructions, DSP data transfer instructions, and DSP operation instructions. This section describes instructions in alphabetical order using the format shown below in section ...

  • Page 144

    Section 6 Instruction Descriptions unsigned short Write_Word(unsigned long Addr, unsigned long Data); unsigned long Write_Long(unsigned long Addr, unsigned long Data); Starts execution from the slot instruction located at an address (Addr – 4). For Delay_Slot (4), execution starts from an ...

  • Page 145

    Definition of bits in SR: #define M ((*(struct SR0 *)(&SR)).M0) #define Q ((*(struct SR0 *)(&SR)).Q0) #define S ((*(struct SR0 *)(&SR)).S0) #define T ((*(struct SR0 *)(&SR)).T0) #define RF1 ((*struct SRO *)(&SR)).RF10) #define RF0 ((*struct SRO *)(&SR)).RF00) Error display function: Error( char ...

  • Page 146

    Section 6 Instruction Descriptions @(disp:8, PC); Indirect PC addressing with displacement disp:8, disp:12:; PC relative addressing 2. 16-bit instruction code that is not assigned as instructions is handled as an ordinary illegal instruction and produces illegal instruction exception processing. Example: ...

  • Page 147

    ADD (ADD Binary): Arithmetic Instruction Format Abstract ADD Rm,Rn #imm, #imm ADD Description: Adds general register Rn data to Rm data, and stores the result in Rn. 8-bit immediate data can be added instead ...

  • Page 148

    Section 6 Instruction Descriptions 6.1.3 ADDC (ADD with Carry): Arithmetic Instruction Format Abstract ADDC Rm,Rn Rn, carry Description: Adds Rm data and the T bit to general register Rn data, and stores the result in ...

  • Page 149

    ADDV (ADD with V Flag Overflow Check): Arithmetic Instruction Format Abstract Rn, ADDV Rm,Rn overflow T Description: Adds general register Rn data to Rm data, and stores the result in Rn overflow occurs, the ...

  • Page 150

    Section 6 Instruction Descriptions Examples: ; Before execution H'00000001 H'7FFFFFFE ADDV R0,R1 ; After execution: ; Before execution H'00000002 H'7FFFFFFE ADDV R0,R1 ; After execution: Rev. ...

  • Page 151

    AND (AND Logical): Logic Operation Instruction Format Abstract Rn & Rm AND Rm,Rn R0 & imm AND #imm,R0 (R0 + GBR) & AND.B #imm, imm (R0 + GBR) @(R0,GBR) Description: Logically ANDs the contents of general registers Rn and ...

  • Page 152

    Section 6 Instruction Descriptions PC+=2; } Examples: AND R0,R1 AND #H'0F,R0 AND.B #H'80,@(R0,GBR) Rev. 5.00 Jun 30, 2004 page 136 of 512 REJ09B0171-0500O ; Before execution H'AAAAAAAA H'55555555 ; After execution H'00000000 ; Before ...

  • Page 153

    BF (Branch if False): Branch Instruction Format Abstract label When disp When nop Description: Reads the T bit, and conditionally branches branches to the ...

  • Page 154

    Section 6 Instruction Descriptions Example: CLRT BT TRGET_T BF TRGET_F NOP NOP .......... TRGET_F: Rev. 5.00 Jun 30, 2004 page 138 of 512 REJ09B0171-0500O ; T is always cleared Does not branch, because ...

  • Page 155

    BF/S (Branch if False with Delay Slot): Branch Instruction Format Abstract BF/S label When disp 2+ PC When nop Description: Reads the T bit and conditionally branches branches ...

  • Page 156

    Section 6 Instruction Descriptions Operation: BFS(long d) /* BFS disp */ { long disp; unsigned long temp; temp=PC; if ((d&0x80)==0) disp=(0x000000FF & (long)d); else disp=(0xFFFFFF00 | (long)d); if (T==0) { PC=PC+(disp<<1); Delay_Slot(temp+2); } else PC+=2; } Example: CLRT BT/S TRGET_T ...

  • Page 157

    BRA (Branch): Branch Instruction Format Abstract label disp BRA Description: Branches unconditionally after executing the instruction following this BRA instruction. The branch destination is an address specified displacement However, in this case it ...

  • Page 158

    Section 6 Instruction Descriptions Example: ; Branches to TRGET BRA TRGET ; Executes ADD before branching ADD R0,R1 ; NOP address of the BRA instruction .......... ; TRGET: Note: With delayed branching, branching occurs after execution of the slot instruction. ...

  • Page 159

    BRAF (Branch Far): Branch Instruction Format Abstract BRAF Rm Description: Branches unconditionally. The branch destination the 32-bit contents of the general register Rm. However, in this case it is used for address ...

  • Page 160

    Section 6 Instruction Descriptions Note: With delayed branching, branching occurs after execution of the slot instruction. However, instructions such as register changes etc. are executed in the order of delayed branch instruction, then delay slot instruction. For example, even if ...

  • Page 161

    BSR (Branch to Subroutine): Branch Instruction Format Abstract PC PR, disp BSR label Description: Branches to the subroutine procedure at a specified address. The PC value is stored in the PR, and the program branches to an address specified ...

  • Page 162

    Section 6 Instruction Descriptions Example: BSR TRGET MOV R3,R4 ADD R0,R1 ....... ....... TRGET: MOV R2,R3 RTS MOV #1,R0 Note: With delayed branching, branching occurs after execution of the slot instruction. However, instructions such as register changes etc. are executed ...

  • Page 163

    BSRF (Branch to Subroutine Far): Branch Instruction Format Abstract PC PR, BSRF Description: Branches to the subroutine procedure at a specified address after executing the instruction following this BSRF instruction. The PC value is ...

  • Page 164

    Section 6 Instruction Descriptions Example: MOV.L #(TARGET-BSRF_PC),R0 BRSF R0 MOV R3,R4 BSRF_PC: ADD R0,R1 ..... ..... TARGET: MOV R2,R3 RTS MOV #1,R0 Note: With delayed branching, branching occurs after execution of the slot instruction. However, instructions such as register changes ...

  • Page 165

    BT (Branch if True): Branch Instruction Format Abstract When label disp When nop Description: Reads the T bit, and conditionally branches branches ...

  • Page 166

    Section 6 Instruction Descriptions Example: SETT BF TRGET_F BT TRGET_T NOP NOP .......... TRGET_T: Rev. 5.00 Jun 30, 2004 page 150 of 512 REJ09B0171-0500O ; T is always 1 ; Does not branch, because Branches to ...

  • Page 167

    BT/S (Branch if True with Delay Slot): Branch Instruction Format Abstract BT/S label When disp When nop Description: Reads the T bit and conditionally branches BT/S ...

  • Page 168

    Section 6 Instruction Descriptions else PC+=2; } Example: SETT BF/S TARGET_F NOP BT/S TARGET_T ADD R0,R1 NOP .......... TARGET_T: Note: With delayed branching, branching occurs after execution of the slot instruction. However, instructions such as register changes etc. are executed ...

  • Page 169

    CLRMAC (Clear MAC Register): System Control Instruction Format Abstract 0 MACH, MACL CLRMAC Description: Clear the MACH and MACL Register. Operation: CLRMAC() /* CLRMAC */ { MACH=0; MACL=0; PC+=2; } Example: ; Clears and initializes the MAC register CLRMAC ...

  • Page 170

    Section 6 Instruction Descriptions 6.1.15 CLRT (Clear T Bit): System Control Instruction Format Abstract 0 T CLRT Description: Clears the T bit. Operation: CLRT() /* CLRT */ { T=0; PC+=2; } Example: ; Before execution: CLRT ; After execution: Rev. ...

  • Page 171

    CMP/cond (Compare Conditionally): Arithmetic Instruction Format Abstract When Rn = Rm, CMP/ Rm, When signed and CMP/ Rm, When signed and CMP/ Rm,Rn Rn > Rm When unsigned CMP/ Rm,Rn ...

  • Page 172

    Section 6 Instruction Descriptions Table 6.1 CMP Mnemonics Mnemonics Condition CMP/EQ Rm, Rm CMP/GE Rm, CMP/GT Rm, > Rm with signed data CMP/HI Rm, > ...

  • Page 173

    CMPHI(long m,long ((unsigned long)R[n]>(unsigned long)R[m]) T=1; else T=0; PC+=2; } CMPHS(long m,long ((unsigned long)R[n]>=(unsigned long)R[m]) T=1; else T=0; PC+=2; } CMPPL(long ((long)R[n]>0) T=1; else T=0; PC+=2; } CMPPZ(long n) /* CMP_PZ ...

  • Page 174

    Section 6 Instruction Descriptions CMPSTR(long m,long n) { unsigned long temp; long HH,HL,LH,LL; temp=R[n]^R[m]; HH=(temp>>12)&0x000000FF; HL=(temp>>8)&0x000000FF; LH=(temp>>4)&0x000000FF; LL=temp&0x000000FF; HH=HH&&HL&&LH&&LL; if (HH==0) T=1; else T=0; PC+=2; } CMPIM(long i) { long imm; if ((i&0x80)==0) imm=(0x000000FF & (long i)); else imm=(0xFFFFFF00 | ...

  • Page 175

    DIV0S (Divide Step 0 as Signed): Arithmetic Instruction Format Abstract MSB DIV0S Rm,Rn MSB M^Q T Description: DIV0S is an initialization instruction for signed division. It finds the quotient by repeatedly dividing in ...

  • Page 176

    Section 6 Instruction Descriptions 6.1.18 DIV0U (Divide Step 0 as Unsigned): Arithmetic Instruction Format Abstract 0 M/Q/T DIV0U Description: DIV0U is an initialization instruction for unsigned division. It finds the quotient by repeatedly dividing in combination with the DIV1 or ...

  • Page 177

    DIV1 (Divide 1 Step): Arithmetic Instruction Format Abstract DIV1 Rm,Rn 1 step division (Rn ÷ Rm) Description: Uses single-step division to divide one bit of the 32-bit data in general register Rn (dividend data (divisor). It finds ...

  • Page 178

    Section 6 Instruction Descriptions Operation: DIV1(long m,long n) { unsigned long tmp0; unsigned char old_q,tmp1; old_q=Q; Q=(unsigned char)((0x80000000 & R[n])!=0); R[n]<<=1; R[n]|=(unsigned long)T; switch(old_q){ case 0:switch(M){ case 0:tmp0=R[n]; R[n]-=R[m]; tmp1=(R[n]>tmp0); switch(Q){ case 0:Q=tmp1; break; case 1:Q=(unsigned char)(tmp1==0); break; } break; ...

  • Page 179

    R[n]+=R[m]; tmp1=(R[n]<tmp0); switch(Q){ case 0:Q=tmp1; break; case 1:Q=(unsigned char)(tmp1==0); break; } break; case 1:tmp0=R[n]; R[n]-=R[m]; tmp1=(R[n]>tmp0); switch(Q){ case 0:Q=(unsigned char)(tmp1==0); break; case 1:Q=tmp1; break; } break; } break; } T=(Q==M); PC+=2; } Section 6 Instruction Descriptions ...

  • Page 180

    Section 6 Instruction Descriptions Example 1: SHLL16 R0 TST R0,R0 BT ZERO_DIV CMP/HS R0,R1 BT OVER_DIV DIV0U .arepeat 16 DIV1 R0,R1 .aendr ROTCL R1 EXTU.W R1,R1 Example 2: TST R0,R0 BT ZERO_DIV CMP/HS R0,R1 BT OVER_DIV DIV0U .arepeat 32 ROTCL ...

  • Page 181

    Example 3: SHLL16 R0 EXTS.W R1,R1 XOR R2,R2 MOV R1,R3 ROTCL R3 SUBC R2,R1 DIV0S R0,R1 .arepeat 16 DIV1 R0,R1 .aendr EXTS.W R1,R1 ROTCL R1 ADDC R2,R1 EXTS.W R1,R1 Example 4: MOV R2,R3 ROTCL R3 SUBC R1,R1 XOR R3,R3 SUBC ...

  • Page 182

    Section 6 Instruction Descriptions 6.1.20 DMULS.L (Double-Length Multiply as Signed): Arithmetic Instruction Format Abstract With sign, Rn DMULS.L Rm, MACH, MACL Rn Description: Performs 32-bit multiplication of the contents of general registers Rn and Rm, and stores the 64-bit results ...

  • Page 183

    Res2=0 Res1=temp1+temp2; if (Res1<temp1) Res2+=0x00010000; temp1=(Res1<<16)&0xFFFF0000; Res0=temp0+temp1; if (Res0<temp0) Res2++; Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3; if (fnLmL<0) { Res2=~Res2; if (Res0==0) Res2++; else Res0=(~Res0)+1; } MACH=Res2; MACL=Res0; PC+=2; } Example: ; Before execution H'FFFFFFFE H'00005555 DMULS.L ...

  • Page 184

    Section 6 Instruction Descriptions 6.1.21 DMULU.L (Double-Length Multiply as Unsigned): Arithmetic Instruction Format Abstract Without sign, DMULU.L Rm MACL Description: Performs 32-bit multiplication of the contents of general registers Rn and Rm, and stores the 64-bit results ...

  • Page 185

    Res0=temp0+temp1; if (Res0<temp0) Res2++; Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3; MACH=Res2; MACL=Res0; PC+=2; } Example: ; Before execution H'FFFFFFFE H'00005555 DMULU.L R0,R1 ; After execution: ; Operation result (top) STS MACH,R0 ; Operation result (bottom) STS MACL,R0 Section 6 Instruction Descriptions ...

  • Page 186

    Section 6 Instruction Descriptions 6.1.22 DT (Decrement and Test): Arithmetic Instruction Format Abstract – 1 Rn; When when Rn is nonzero Description: The contents of general register Rn are decremented ...

  • Page 187

    EXTS (Extend as Signed): Arithmetic Instruction Format Abstract Sign-extend Rm EXTS.B Rm, from byte Rn Rn Sign-extend Rm EXTS.W Rm, from word Rn Description: Sign-extends general register Rm data, and stores the result in Rn. If byte length is ...

  • Page 188

    Section 6 Instruction Descriptions Examples: ;Before execution H'00000080 EXTS.B R0,R1 ;After execution: ;Before execution H'00008000 EXTS.W R0,R1 ;After execution: Rev. 5.00 Jun 30, 2004 page 172 of 512 REJ09B0171-0500O R1 = H'FFFFFF80 R1 = H'FFFF8000 ...

  • Page 189

    EXTU (Extend as Unsigned): Arithmetic Instruction Format Abstract Zero-extend Rm EXTU.B Rm, from byte Rn Rn Zero-extend Rm EXTU.W Rm, from word Rn Description: Zero-extends general register Rm data, and stores the result in Rn. If byte length is ...

  • Page 190

    Section 6 Instruction Descriptions 6.1.25 JMP (Jump): Branch Instruction Class: Delayed branch instruction Format Abstract Rm PC JMP @Rm Description: Branches unconditionally to the address specified by register indirect addressing. The branch destination is an address specified by the 32-bit ...

  • Page 191

    JSR (Jump to Subroutine): Branch Instruction (Class: Delayed Branch Instruction) Format Abstract @Rm PC PR, Rm JSR Description: Branches to the subroutine procedure at the address specified by register indirect addressing. The PC value is stored in the PR. ...

  • Page 192

    Section 6 Instruction Descriptions Example: MOV.L JSR_TABLE,R0 JSR @R0 XOR R1,R1 ADD R0,R1 ........... .align 4 JSR_TABLE: .data.l TRGET TRGET: NOP MOV R2,R3 RTS MOV #70,R1 Note: When a delayed branch instruction is used, the branching operation takes place after ...

  • Page 193

    LDC (Load to Control Register): System Control Instruction (Class: Interrupt Disabled Instruction) Format Abstract Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm MOD LDC Rm,MOD Rm RE LDC Rm, LDC Rm,RS (Rm) ...

  • Page 194

    Section 6 Instruction Descriptions LDCVBR(long m) /* LDC Rm,VBR */ { VBR=R[m]; PC+=2; } LDCMOD(long m) /* LDC Rm,MOD */ { MOD=R[m]; PC+=2; } LDCRE(long m) /* LDC Rm, RE=R[m]; PC+=2; } LDCRS(long m) /* LDC Rm,RS */ ...

  • Page 195

    LDCMVBR(long m) { VBR=Read_Long(R[m]); R[m]+=4; PC+=2; } LDCMMOD(long m) { MOD=Read_Long(R[m]); R[m]+=4; PC+=2; } LDCMRE(long m) { RE=Read_Long(R[m]); R[m]+=4; PC+=2; } LDCMRS(long m) { RS=Read_Long(R[m]); R[m]+=4; PC+=2; } Examples: ; Before execution H'FFFFFFFF H'00000000 LDC R0,SR ...

  • Page 196

    Section 6 Instruction Descriptions 6.1.28 LDRE (Load Effective Address to RE Register): System Control Instruction Format Abstract LDRE @(disp,PC) disp Description: Stores the effective address of the source operand in the repeat end register RE. The ...

  • Page 197

    Example: LDRS STA LDRE END SETRC #32 inst.0 STA: inst.A inst.B ............ END: inst.C inst.E ............ ; Set repeat start address to RS. ; Set repeat end address to RE. ; Repeat 32 times from inst.A to inst. ...

  • Page 198

    Section 6 Instruction Descriptions 6.1.29 LDRS (Load Effective Address to RS Register): System Control Instruction Format Abstract LDRS @(disp,PC) disp Description: Stores the effective address of the source operand in the repeat start register RS. The ...

  • Page 199

    Example: LDRS STA LDRE END SETRC #32 inst.0 STA: inst.A inst.B ............ END: inst.C inst.D ............ ; Set repeat start address to RS. ; Set repeat end address to RE. ; Repeat 32 times from inst.A to inst. ...

  • Page 200

    Section 6 Instruction Descriptions 6.1.30 LDS (Load to System Register): System Control Instruction Class: Interrupt disabled instruction Format Abstract Rm,MACH Rm MACH LDS Rm,MACL Rm MACL LDS Rm PR LDS Rm,PR Rm DSR LDS Rm,DSR Rm A0 LDS Rm,A0 Rm ...