HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 156

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
Operation:
Example:
Rev. 5.00 Jun 30, 2004 page 140 of 512
REJ09B0171-0500O
BFS(long d)
{
}
TRGET_F:
Note: With delayed branching, branching occurs after execution of the slot instruction.
long disp;
unsigned long temp;
temp=PC;
if ((d&0x80)==0) disp=(0x000000FF & (long)d);
else disp=(0xFFFFFF00 | (long)d);
if (T==0) {
}
else PC+=2;
However, instructions such as register changes etc. are executed in the order of delayed
branch instruction, then delay slot instruction. For example, even if the register in which
the branch destination address has been loaded is changed by the delay slot instruction,
the branch will still be made using the value of the register prior to the change as the
branch destination address.
PC=PC+(disp<<1);
Delay_Slot(temp+2);
CLRT
BT/S TRGET_T
NOP
BF/S TRGET_F
ADD
NOP
..........
/* BFS disp */
R0,R1
; T is always 0
; Does not branch, because T = 0
;
; Branches to TRGET_F, because T = 0
; Executed before branch
;
address of the BF/S instruction
;
The PC location is used to calculate the branch destination
Branch destination of the BF/S instruction
.