HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 163

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.1.11
Description: Branches to the subroutine procedure at a specified address after executing the
instruction following this BSRF instruction. The PC value is stored in the PR. The branch
destination is PC + the 32-bit contents of the general register Rm. However, in this case it is used
for address calculation. The PC is the address 4 bytes after this instruction. Used as a subroutine
procedure call in combination with RTS.
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
Operation:
Format
BSRF Rm
BSRF(long m) /* BSRF Rm */
{
}
PR=PC+Is_32bit_Inst(PR+2);
PC+=R[m];
Delay_Slot(PR+2);
branching. No interrupts and address errors are accepted between this instruction and the
next instruction. If the next instruction is a branch instruction, it is acknowledged as an
illegal slot instruction.
BSRF (Branch to Subroutine Far): Branch Instruction
Abstract
PC
Rm + PC
PR,
PC
Code
0000mmmm00000011 2
Rev. 5.00 Jun 30, 2004 page 147 of 512
Cycle T Bit SH-1 SH-2
Section 6 Instruction Descriptions
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP

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