HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 17

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
1.1
The SH-1 and SH-2 CPU have RISC-type instruction sets. Basic instructions are executed in one
clock cycle, which dramatically improves instruction execution speed. The CPU also has an
internal 32-bit architecture for enhanced data processing ability. Table 1.1 lists the SH-1 and SH-2
CPU features.
Table 1.1
Item
Architecture
General-register machine
Instruction set
Instruction execution time
Address space
On-chip multiplier
(SH-1 CPU)
On-chip multiplier
(SH-2 CPU)
Pipeline
SH-1 and SH-2 Features
SH-1 and SH-2 CPU Features
Feature
Original Renesas Technology architecture
32-bit internal data bus
Sixteen 32-bit general registers
Three 32-bit control registers
Four 32-bit system registers
Instruction length: 16-bit fixed length for improved code efficiency
Load-store architecture (basic arithmetic and logic operations are
executed between registers)
Delayed branch system used for reduced pipeline disruption
Instruction set optimized for C language
One instruction/cycle for basic instructions
Architecture makes 4 Gbytes available
Multiplication operations (16 bits
to 3 cycles, and multiplication/accumulation operations (16 bits
bits + 42 bits
Multiplication operations executed in 1 to 2 cycles (16 bits
multiplication/accumulation operations executed in 3/(2)* cycles (16
bits
bits + 64 bits
Five-stage pipeline
Section 1 Features
32 bits) or 2 to 4 cycles (32 bits
16 bits + 64 bits
42 bits) executed in 3/(2)* cycles
64 bits)
64 bits) or 3/(2 to 4)* cycles (32 bits
Rev. 5.00 Jun 30, 2004 page 1 of 512
16 bits
32 bits
32 bits) executed in 1
64 bits), and
REJ09B0171-0500O
Section 1 Features
16 bits
32
16

Related parts for HD6417041AVF16V