HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 225

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.1.36
Description: Transfers the source operand to the destination. This instruction is optimum for
accessing data in a structure or a stack. The data can be a byte, word, or longword, but when a byte
or word is selected, only the R0 register can be used. When the data is a byte, the only change
made is to zero-extend the 4-bit displacement. Consequently, an address within +15 bytes can be
specified. When the data is a word, the 4-bit displacement is zero-extended and doubled.
Consequently, an address within +30 bytes can be specified. When the data is a longword, the
4-bit displacement is zero-extended and quadrupled. Consequently, an address within +60 bytes
can be specified. If the displacement is too short to reach the memory operand, the aforementioned
@(R0,Rn) mode must be used. When the source operand is in memory, the loaded data is stored in
the register after it is sign-extended to a longword.
Note: When byte or word data is loaded, the destination register is always R0. R0 cannot be
Format
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
R0,@(disp,Rn)
R0,@(disp,Rn)
Rm,@(disp,Rn)
@(disp,Rm),R0
@(disp,Rm),R0
@(disp,Rm),Rn
accessed by the next instruction until the load instruction is finished. The instruction order
in figure 6.2 will give better results.
MOV (Move Structure Data): Data Transfer Instruction
MOV.B
AND
ADD
Abstract
R0
R0
Rm
(disp + Rm)
extension
(disp
extension
disp
(disp + Rn)
(disp
4 + Rm)
(disp
2 + Rm)
@(2, R1), R0
#80, R0
#20, R1
Figure 6.2 Using R0 after MOV
R0
R0
2 + Rn)
4 + Rn)
sign
Rn
sign
Code
10000000nnnndddd
10000001nnnndddd
0001nnnnmmmmdddd
10000100mmmmdddd
10000101mmmmdddd
0101nnnnmmmmdddd
MOV.B
ADD
AND
Rev. 5.00 Jun 30, 2004 page 209 of 512
Section 6 Instruction Descriptions
@(2, R1), R0
#20, R1
#80, R0
Cycle
1
1
1
1
1
1
T
Bit SH-1
—
—
—
—
—
—
REJ09B0171-0500O
Instructions
Applicable
SH-2
SH-
DSP