HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 24

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 Register Configuration
As0:
As1:
As2:
As3:
Is:
2.2
The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR),
and vector base register (VBR) (figure 2.3). The status register indicates processing states. The
global base register functions as a base address for the indirect GBR addressing mode to transfer
data to the registers of on-chip peripheral modules. The vector base register functions as the base
address of the exception processing vector area (including interrupts).
Rev. 5.00 Jun 30, 2004 page 8 of 512
REJ09B0171-0500O
SR
31
31
31
.REG
.REG
.REG
.REG
.REG
Control Registers
(R4); defined when an alias is needed for a single data transfer.
(R5); defined when an alias is needed for a single data transfer.
(R2); defined when an alias is needed for a single data transfer.
(R3); defined when an alias is needed for a single data transfer.
(R8); defined when an alias is needed for a single data transfer.
Figure 2.3 Control Registers (SH-1 and SH-2)
GBR
VBR
M Q I3 I2 I1 I0
9 8 7 6 5 4 3 2 1 0
S T
0
0
SR: Status register
T bit: The MOVT, CMP/cond, TAS, TST,
S bit: Used by the multiply/accumulate
Reserved bits: Always reads as 0, and should
always be written with 0.
Bits I3–I0: Interrupt mask bits.
M and Q bits: Used by the DIV0U/S and
Global base register (GBR):
Indicates the base address of the indirect
GBR addressing mode. The indirect GBR
addressing mode is used in data transfer
for on-chip peripheral module register
areas and in logic operations.
Vector base register (VBR):
Indicates the base address of the exception
processing vector area.
BT (BT/S), BF (BF/S), SETT, and CLRT
instructions use the T bit to indicate
true (1) or false (0). The ADDV/C,
SUBV/C, DIV0U/S, DIV1, NEGC,
SHAR/L, SHLR/L, ROTR/L, and
ROTCR/L instructions also use bit T
to indicate carry/borrow or overflow/
underflow
instruction.
DIV1 instructions.