HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 245

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.1.51
Class: Delayed branch instruction
Description: Returns from an interrupt routine. The PC and SR values are restored from the stack,
and the program continues from the address specified by the restored PC value. The T bit is used
as the LSB bit in the SR register restored from the stack area.
Note: Since this is a delayed branch instruction, the instruction after this RTE is executed before
Operation:
Example:
Format
RTE
RTE() /* RTE */
{
}
RTE
ADD
unsigned long temp;
temp=PC;
PC=Read_Long(R[15])+4;
R[15]+=4;
SR=Read_Long(R[15])&0x0FFF0FFF;
R[15]+=4;
Delay_Slot(temp+2);
branching. No address errors and interrupts are accepted between this instruction and the
next instruction. If the next instruction is a branch instruction, it is acknowledged as an
illegal slot instruction.
#8,R14
RTE (Return from Exception): System Control Instruction
Abstract
Delayed branch,
Stack area
; Returns to the original routine
; Executes ADD before branching
PC/SR
Code
0000000000101011 4
Rev. 5.00 Jun 30, 2004 page 229 of 512
Cycle T Bit
Section 6 Instruction Descriptions
LSB
SH-1 SH-2
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP