HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 28

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 Register Configuration
In addition, the SH-DSP also uses as its system registers the DSP status register (DSR) and five of
the eight data registers (A0, X0, X1, Y0, Y1), which are all registers of the DSP unit and will be
described later (DSP registers). The A0 register is a 40-bit register, but the guard bit section (A0G)
is ignored in data read from A0. When data is input to the A0 register, the MSB of the data is
copied to the guard bit section (A0G).
2.4
DSP Registers
The DSP unit has nine DSP registers, divided into eight data registers and one control register.
The DSP data registers include two 40-bit registers (A0 and A1) and six 32-bit registers (M0, M1,
X0, X1, Y0, and Y1). The A1 and A0 registers each has eight guard bits, A0G and A1G.
The DSP data registers are used in transferring and processing DSP data as the operand for the
DSP instruction. There are three types of instructions that access the DSP data registers: DSP data
processing, X data processing, and Y data processing.
The 32-bit DSP status register (DSR) is the control register, which indicates the results of
operations. The DSR register has bits to display the results of the operation, which include a
signed greater than bit (GT), a zero value bit (Z), a negative value bit (N), an overflow bit (V), a
DSP condition bit (DC), and condition select bits, which control the DC bit settings (CS).
The DC bit is one of the status flags; it is very similar to the SuperH CPU core’s T bit. In the case
of conditional DSP type instructions, the execution of DSP data processing is controlled in
accordance with the DC bit. This control is related to DSP unit execution only, and only the DSP
registers are updated. It is not related to the execution instructions of the SuperH microprocessor’s
CPU core, such as address calculation and load/store instructions. The control bits CS (bits 0 to 2)
specify the condition that the DC bits set.
DSP instructions include both unconditional DSP instructions and conditioned DSP instructions.
Data processing of unconditional DSP instructions updates the condition bits and DC bits, except
for the PMULS, PWAD, PWSB, MOVX, MOVY, and MOVS instructions. Conditional DSP type
instructions are executed in accordance with the status of the DC bit. DSR registers are not
updated, regardless of whether these instructions are executed or not.
Note that five registers, A0, X0, X1, Y0, and Y1, can also be used as system registers.
Figure 2.6 shows the DSP registers. Table 2.2 lists the DSR register bit functions.
Rev. 5.00 Jun 30, 2004 page 12 of 512
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