HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 30

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 Register Configuration
Table 2.2
Bits
31–8
7
6
5
4
3–1
0
CPU core instructions use the A0, X0, X1, Y0, Y1, and DSR registers as a system registers.
2.5
Data operation in the DSP unit is basically executed in 32 bits. Actual operation, however, is made
in 40-bit length including 8 guard bits. When the guard bits are inconsistent with the value of MSB
of 32 bits, the operation result is handled as overflow. In this case, the N bit indicates the correct
condition of the operation result whether overflow has occurred or not. This is also the same when
the destination operand is a register of 32 bits in length. Each status flag is updated always
assuming guard bits of 8 bits.
If line overflow occurs so that the result is not correctly indicated even though the guard bits are
used, the N flag cannot show the correct condition. Refer to section 8.1, ALU Fixed Decimal Point
Operation, DC Bit, for details.
Rev. 5.00 Jun 30, 2004 page 14 of 512
REJ09B0171-0500O
Name
Reserved
Signed greater than bit
(GT)
Zero value bit (Z)
Negative value bit (N)
Overflow bit (V)
Condition select bits
(CS)
DSP condition bit (DC)
Precautions for Handling of Guard Bit and Overflow
DSR Register Bits
Function
0: Always reads 0. Always write 0.
Indicates whether the operation result is positive (and
nonzero) or whether operand 1 is larger than operand 2.
1: Operation result is positive or operand 1 is larger.
Indicates whether the operation result is zero or whether of
operands 1 and 2 are the same.
1: Operation result is zero or operands 1 and 2 are the same.
Indicates whether the operation result is negative or whether
operand 1 is smaller than operand 2.
1: Operation result is negative or operand 1 is smaller.
1: Operation result overflowed.
Specifies the mode for selecting the status of the operation
result set in the DC bit. Do not specify 110 or 111.
000: Carry/borrow mode
001: Negative value mode
010: Zero value mode
011: Overflow mode
100: Signed greater than mode
101: Signed equal or greater than mode
Sets the operation result status in the mode specified by the
CS bits.
0: Specified mode status not achieved
1: Specified mode status achieved.
Indicates that the operation result overflowed.