HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 428

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Pipeline Operation
7.1.4
The number of instruction execution cycles is counted as the interval between execution of EX
stages. The number of cycles between the start of the EX stage for instruction 1 and the start of the
EX stage for the following instruction (instruction 2) is the execution time for instruction 1.
For example, in a pipeline flow like that shown in figure 7.5, the EX stage interval between
instructions 1 and 2 is five cycles, so the execution time for instruction 1 is five cycles. Since the
interval between EX stages for instructions 2 and 3 is one cycle, the execution time of instruction
2 is one cycle.
If a program ends with instruction 3, the execution time for instruction 3 should be calculated as
the interval between the EX stage of instruction 3 and the EX stage of a hypothetical instruction 4,
using a MOV Rm, Rn that follows instruction 3. (In figure 7.5, the execution time of instruction 3
would thus be one cycle.) In this example, the MA of instruction 1 and the IF of instruction 4 are
in contention. For operation during the contention between the MA and IF, see section 7.2.1,
Contention between Instruction Fetch (IF) and Memory Access (MA).
Rev. 5.00 Jun 30, 2004 page 412 of 512
REJ09B0171-0500O
(Instruction 4
Instruction 1
Instruction 2
Instruction 3
Number of Instruction Execution Cycles
Figure 7.5 Method for Counting Instruction Execution Cycles
: MOV Rm, Rn
(2)
IF
IF
(2)
ID
IF
—
IF
EX
(2)
ID
IF
—
—
IF
MA MA MA W/D
(4)
—
—
—
—
—
—
EX
ID
IF
EX
(1)
ID
MA
EX
(1)
)
: Slot